| title | author | taken |
| Radiation-Hardened Flip-Flops in a 65 nm Bulk Process for Terrestrial Applications Coping With Radiation Hardness and Performance Overheads,pdf | S. Sugitani, R. Nakajima, K. Yoshida, J. Furuta, and K. Kobayashi | IEICE Trans. on Electronics, vol.E108-C (Early Access), no. 2, 2024/07 |
| Frequency Dependence of Soft Error Rates Induced by Alpha- particle and Heavy Ion,pdf[URL] | H. Sugisaki, R. Nakajima, S. Sugitani, J. Furuta, and K. Kobayashi | IEICE Electronics Express, vol.Early Access, 2024/05 |
| Measuring SET Pulse Widths in pMOSFETs and nMOSFETs Separately by Heavy-ion and Neutron Irradiation,pdf[URL] | J. Furuta, S. Sugitani, R. Nakajima, T. Ito, and K. Kobayashi | IEICE Trans. on Electronics, vol.(Early Access), 2024/04 |
| Soft-error Tolerance by Guard-Gate Structures on Flip-Flops in 22 and 65 nm FD-SOI Technologies,pdf[URL] | R. Nakajima, T. Ito, S. Sugitani, T. Kii, M. Ebara, J. Furuta, K. Kobayashi, M. Louvat, F. Jacquet, J. Eloy, O. Montfort, J. Lionel, and V. Huard | IEICE Trans. on Electronics, 2024/02 |
| The Contribution of Secondary Particles following Carbon Ion Radiotherapy to Soft Errors in CIEDs,pdf[URL] | Y. Kawakami, M. Sakai, H. Masuda, M. Miyajima, T. Kanzaki, K. Kobayashi, T. Ohno, and H. Sakurai | IEEE Open Journal of Engineering in Medicine and Biology, vol.5, pp. 157-162, 2024/01 |
| Nonvolatile Storage Cells Using FiCC for IoT Processors with Intermittent Operations,pdf[URL] | Y. Abe, K. Kobayashi, J. Shiomi, and O. Hiroyuki | IEICE Trans. on Electronics, vol.E106, no. 10, pp. 546-555, 2023/10 |
| A Terrestrial SER Estimation Methodology based on Simulation coupled with One-Time Neutron Irradiation Testing,pdf[URL] | S. Abe, M. Hashimoto, W. Liao, T. Kato, H. Asai, K. Shimbo, H. Matsuyama, T. Sato, K. Kobayashi, and Y. Watanabe | IEEE Trans. on Nuclear Science, vol.70, no. 8, pp. 1652-1657, 2023/05 |
| A Three-Level GaN Driver for High False Turn-ON Tolerance with Minimal Reverse Conduction Loss,pdf[URL] | T. Takahashi, T. Takehisa, J. Furuta, M. Shintani, and K. Kobayashi | IEEE Open Journal of Power Electronics, vol.4, pp. 357-366, 2023/05 |
| Disturbance Aware Dynamic Power Reduction in Synchronous 2RW Dual-Port 8T SRAM by Self-Adjusting Wordline Pulse Timing,pdf[URL] | Y. Yokoyama, K. Nii, Y. Ishii, S. Tanaka, and K. Kobayashi | Journal of Solid-State Circuits, vol.58, no. 7, pp. 2098-2108, 2022/12 |
| A Bit-Error Rate Measurement and Error Analysis of Wireline Data Transmission using Current Source Model for Single Event Effect under Irradiation Environment,pdf[URL] | T. Yoshikawa, M. Ishimaru, T. Iwata, and K. Kobayashi | Journal of Electronic Testing, vol.37, no. 5, 2022/01 |
| Cost-Effective Test Screening Method on 40-nm Embedded SRAMs for Low-power MCUs,pdf[URL] | Y. Yokoyama, Y. Ishii, K. Nii, and K. Kobayashi | IEEE Transactions On Very Large Scale Integration (VLSI) Systems, vol.29, no. 7, pp. 1495 - 1499, 2021/06 |
| An Analysis of Local BTI Variation with Ring-Oscillator in Advanced Processes and Its Impact on Logic Circuit and SRAM,pdf[URL] | M. Igarashi, Y. Uchida, Y. Takazawa, M. Yabuuchi, Y. Tsukamoto, K. Shibutani, and K. Kobayashi | IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol.E104.A , no. 11, pp. 1536-1545, 2021/05 |
| Intrinsic Vulnerability to Soft Errors and a Mitigation Technique by Layout Optimization on DICE Flip Flops in a 65 nm Bulk Process,pdf[URL] | F. Mori, M. Ebara, Y. Tsukita, J. Furuta, and K. Kobayashi | IEEE Trans. on Nuclear Science, vol.68, no. 8, pp. 1727-1735, 2021/04 |
| An E-mode p-GaN HEMT Monolithically-Integrated Three-level Gate Driver Operating with a Single Voltage Supply,pdf[URL] | J. Nagao, U. Chatterjee, X. Li, J. Furuta, D. Stefaan, and K. Kobayashi | IEICE Electronics Express, vol.18, no. 6, pp. 20210059, 2021/03 |
| Universal NBTI Compact Model Replicating AC Stress/Recovery from a Single-shot Long-term DC Measurement,pdf[URL] | T. Hosaka, S. Nishizawa, R. Kishida, T. Matsumoto, and K. Kobayashi | IPSJ Transactions on System LSI Design Methodology, vol.13, pp. 56-64, 2020/08 |
| Evaluation of Soft-Error Tolerance by Neutrons and Heavy Ions on Flip Flops with Guard Gates in a 65 nm Thin BOX FDSOI Process,pdf[URL] | M. Ebara, K. Yamada, K. Kojima, Y. Tsukita, J. Furuta, and K. Kobayashi | IEEE Trans. on Nuclear Science, vol.67, no. 7, pp. 1470 - 1477, 2020/06 |
| Evaluation of Heavy-Ion-Induced Single Event Upset Cross Sections of a 65-nm Thin BOX FD-SOI Flip-Flops Composed of Stacked Inverters,pdf[URL] | K. Kojima, K. Yamada, J. Furuta, and K. Kobayashi | IEICE Trans. on Electronics, vol.E103-C, no. 4, pp. 144-152, 2020/04 |
| Extracting Voltage Dependence of BTI-induced Degradation without Temporal Factors by Using BTI-Sensitive and BTI-Insensitive Ring Oscillators,pdf[URL] | R. Kishida, T. Asuke, J. Furuta, and K. Kobayashi | IEEE Transacition on Semiconductor Manufacturing, vol.33, no. 2, pp. 174-179, 2020/03 |
| Characterizing SRAM and FF soft error rates with measurement and simulation,pdf[URL] | M. Hashimoto, K. Kobayashi, S. Abe, Y. Watanabe, and J. Furuta | Journal of Integration, vol.69, pp. 161-179, 2019/11 |
| Monolithic integration of gate driver and p-GaN power HEMT for MHz-switching implemented by e-mode GaN-on-SOI process,pdf[URL] | Y. Yamashita, S. Stoffels, P. Niels, K. Geens, X. Li, J. Furuta, D. Stefaan, and K. Kobayashi | IEICE Electronics Express, vol.16, no. 22, pp. 20190516, 2019/10 |
| Radiation-Hardened Structure to Reduce Sensitive Range of a Stacked Structure for FDSOI,pdf[URL] | K. Yamada, M. Ebara, K. Kojima, Y. Tsukita, J. Furuta, and K. Kobayashi | IEEE Trans. on Nuclear Science, vol.66, no. 7, pp. 1418-1426, 2019/04 |
| Process Dependence of Soft Errors Induced by α Particles, Heavy Ions, and High Energy Neutrons on Flip Flops in FDSOI,pdf[URL] | M. Ebara, K. Yamada, K. Kojima, J. Furuta, and K. Kobayashi | Journal of the Electron Device Society, vol.7, no. 1, pp. 817-824, 2019/03 |
| An Efficient and Accurate Time Step Control Method for Power Device Transient Simulation Utilizing Dominant Time Constant Approximation,pdf[URL] | S. Kumashiro, T. Kamei, A. Hiroki, and K. Kobayashi | IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol.39, no. 2, pp. 451-463, 2018/12 |
| Radiation-Hardened Flip-Flops with Low-Delay Overhead Using PMOS Pass-Transistors to Suppress SET Pulses in a 65 nm FDSOI Process,pdf[URL] | K. Yamada, H. Maruoka, J. Furuta, and K. Kobayashi | IEEE Trans. on Nuclear Science, vol.65, no. 8, pp. 1814-1822 , 2018/04 |
| A Low-Power Radiation-Hardened Flip-Flop with Stacked Transistors in a 65 nm FDSOI Process,pdf[URL] | H. Maruoka, M. Hifumi, J. Furuta, and K. Kobayashi | IEICE Trans. on Electronics, vol.101-C, no. 4, pp. 273-280, 2018/04 |
| Evaluation of plasma-induced damage and bias temperature instability depending on type of antenna layer using current-starved ring oscillators,pdf[URL] | R. Kishida, J. Furuta, and K. Kobayashi | Japanese Journal of Applied Physics, vol.57, no. 4s, pp. 04FD12-1-5, 2018/03 |
| Replication of Random Telegraph Noise by Using a Physical-Based Verilog-AMS Model,pdf[URL] | T. Komawaki, M. Yabuuchi, R. Kishida, J. Furuta, T. Matsumoto, and K. Kobayashi | IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol.E-100A, no. 12, pp. 2758-2763, 2017/12 |
| Analysis of Soft Error Rates in 65- and 28-nm FD-SOI Processes Depending on BOX Region Thickness and Body Bias by Monte-Carlo Based Simulations,pdf[URL] | K. Zhang, S. Umehara, J. Yamaguchi, J. Furuta, and K. Kobayashi | IEEE Trans. on Nuclear Science, vol.63, no. 4, pp. 2002-2009, 2016/08 |
| A Radiation-Hardened Non-Redundant Flip-Flop, Stacked Leveling Critical Charge Flip-Flop in a 65 nm Thin BOX FD-SOI Process,pdf[URL] | J. Furuta, J. Yamaguchi, and K. Kobayashi | IEEE Trans. on Nuclear Science, vol.63, no. 4, pp. 2080-2086, 2016/08 |
| Size Optimization Technique for Logic Circuits that Considers BTI and Process Variations,pdf[URL] | M. Yabuuchi, and K. Kobayashi | IPSJ Transactions on System LSI Design Methodology, vol.9, pp. 72-78, 2016/08 |
| A Perpetuum Mobile 32bit CPU on 65nm SOTB CMOS Technology with Reverse-Body-Bias Assisted Sleep Mode,pdf[URL] | K. Ishibashi, N. Sugii, S. Kamohara, K. Usami, A. Hideharu, K. Kobayashi, and P. Cong-Kha | IEICE Trans. on Electronics, vol.E98-C, no. 7, pp. 536-543, 2015/07 |
| Impact of Cell Distance and Well-contact Density on Neutron-induced Multiple Cell Upsets,pdf[URL] | J. Furuta, K. Kobayashi, and H. Onodera | IEICE Trans. on Electronics, vol.E98-C, no. 4, pp. 1745-1353, 2015/04 |
| Initial and long-term frequency degradation of ring oscillators caused by plasma-induced damage in 65 nm bulk and fully depleted silicon-on-insulator processes ,pdf[URL] | R. Kishida, A. Oshima, M. Yabuuchi, and K. Kobayashi | Japanese Journal of Applied Physics, vol.54, no. 4S, pp. 04DC19-1-5, 2015/03 |
| Radiation hardness evaluations of 65nm fully depleted silicon on insulator and bulk processes by measuring single event transient pulse widths and single event upset rates,pdf[URL] | J. Furuta, E. Sonezaki, and K. Kobayashi | Japanese Journal of Applied Physics, vol.54, no. 4S, pp. 04DC15-1-6, 2015/03 |
| Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing,pdf[URL] | H. Kounoura, D. Dawood, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, O. Hiroyuki, T. Imagawa, K. Wakabayashi, M. Hashimoto, T. Onoye, and H. Onodera | IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol.E97-A, no. 12, pp. 2518-2529, 2014/12 |
| EReLA: A Low-Power Reliable Coarse-Grained Reconfigurable Architecture Processor and Its Irradiation Tests ,pdf[URL] | J. Yao, M. Saito, S. Okada, K. Kobayashi, and Y. Nakashima | IEEE Trans. on Nuclear Science, vol.61, no. 6, pp. 3250-3257, 2014/12 |
| Correlations between BTI-Induced Degradations and Process Variations on ASICs and FPGAs,pdf[URL] | M. Yabuuchi, R. Kishida, and K. Kobayashi | IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol.E97-A, no. 12, pp. 2367-2372, 2014/12 |
| Dependence of Cell Distance and Well-Contact Density on MCU Rates by Device Simulations and Neutron Experiments in a 65-nm Bulk Process ,pdf | K. Zhang, J. Furuta, K. Kobayashi, and H. Onodera | IEEE Trans. on Nuclear Science, vol.61, no. 4, pp. 1583-1589, 2014/08 |
| A Low-Power and Area-Efficient Radiation-Hard Redundant Flip-Flop, DICE ACFF, in a 65 nm Thin-BOX FD-SOI ,pdf[URL] | K. Kobayashi, K. Kubota, M. Masuda, Y. Manzawa, J. Furuta, S. Kanda, and H. Onodera | IEEE Trans. on Nuclear Science, vol.61, no. 4, pp. 1881-1888, 2014/08 |
| A 65 nm Low-Power Adaptive-Coupling Redundant Flip-Flop,pdf[URL] | M. Masuda, K. Kubota, R. Yamamoto, J. Furuta, K. Kobayashi, and H. Onodera | IEEE Trans. on Nuclear Science, vol.60, no. 4, pp. 2750 - 2755 , 2013/08 |
| Structural Dependence of Source-and-Drain Series Resistance on Saturation Drain Current for Sub-20 nm Metal-Oxide-Semiconductor Field-Effect Transistors,pdf[URL] | J. Yoon, A. Hiroki, and K. Kobayashi | Japanese Journal of Applied Physics, vol.52, no. 7R, pp. 071302, 2013/06 |
| A Radiation-Hard Redundant Flip-Flop to Suppress Multiple Cell Upset by Utilizing the Parasitic Bipolar Effect,pdf[URL] | K. Zhang, J. Furuta, R. Yamamoto, K. Kobayashi, and H. Onodera | IEICE Trans. on Electronics, vol.E96-C, no. 2, pp. 511-517, 2013/04 |
| Impact of Body-Biasing Technique on Random Telegraph Noise Induced Delay Fluctuation,pdf[URL] | T. Matsumoto, K. Kobayashi, and H. Onodera | Japanese Journal of Applied Physics, vol.52, pp. 04CE05, 2013/03 |
| Effects of Neutron-Induced Well Potential Perturbation for Multiple Cell Upset of Flip-Flops in 65 nm,pdf[URL] | J. Furuta, R. Yamamoto, K. Kobayashi, and H. Onodera | IEEE Trans. on Nuclear Science, vol.60, no. 1, pp. 213-218, 2013/01 |
| Higher-Order Effect of Source-Drain Series Resistance on Saturation Drain Current in Sub-20nm Metal-Oxide-Semiconductor Field-Effect Transistors,pdf[URL] | J. Yoon, A. Hiroki, and K. Kobayashi | Japanese Journal of Applied Physics, vol.51, pp. 111101-1-111101-5, 2012/12 |
| DARA: A Low-Cost Reliable Architecture Based on Unhardened Devices and Its Case Study of Radiation Stress Test ,pdf[URL] | J. Yao, S. Okada, M. Masuda, K. Kobayashi, and Y. Nakashima | IEEE Trans. on Nuclear Science, vol.59, no. 6, pp. 2852 - 2858 , 2012/12 |
| NBTI-Induced Delay Degradation Analysis of FPGA Routing Structures ,pdf[URL] | M. Yabuuchi, and K. Kobayashi | IPSJ Transactions on System LSI Design Methodology, vol.5, pp. 143-149, 2012/08 |
| Variation-Sensitive Monitor Circuits for Estimation of Global Process Parameter Variation,pdf[URL] | I. A.K.M Mahfuzul, A. Tsuchiya, K. Kobayashi, and H. Onodera | IEEE Transacition on Semiconductor Manufacturing, vol.25, no. 4, pp. 571-580, 2012/05 |
| Multicore Large-Scale Integration Lifetime Extension by Negative Bias Temperature Instability Recovery-Based Self-Healing,pdf[URL] | T. Matsumoto, H. Makino, K. Kobayashi, and H. Onodera | Japanese Journal of Applied Physics, vol.51, no. 4, 2012/04 |
| An Area-efficient 65 nm Radiation-Hard Dual-Modular Flip-Flop to Avoid Multiple Cell Upsets,pdf[URL] | R. Yamamoto, C. Hamanaka, J. Furuta, K. Kobayashi, and H. Onodera | IEEE Trans. on Nuclear Science, vol.58, no. 6, pp. 3053 - 3059, 2011/12 |
| Variation-Tolerance of a 65-nm Error-Hardened Dual-Modular-Redundancy Flip-Flop Measured by Shift-Register-Based Monitor Structures,pdf[URL] | C. Hamanaka, R. Yamamoto, J. Furuta, K. Kubota, K. Kobayashi, and H. Onodera | IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol.E94-A, no. 12, pp. 2669-2675, 2011/12 |
| A 65 nm Complementary Metal-Oxide-Semiconductor 400 ns Measurement Delay Negative-Bias-Temperature-Instability Recovery Sensor with Minimum Assist Circuit,pdf[URL] | T. Matsumoto, H. Makino, K. Kobayashi, and H. Onodera | Japanese Journal of Applied Physics, vol.50, no. 4, pp. 04DE06, 2011/04 |
| An Area/Delay Efficient Dual-Modular Flip-Flop with Higher SEU/SET Immunity,pdf[URL] | J. Furuta, K. Kobayashi, and H. Onodera | IEICE Trans. on Electronics, vol.E93-C, no. 2, pp. 340-346, 2010/03 |
| Effect of Regularity-Enhanced Layout on Variability and Circuit Performance of Standard Cells,pdf[URL] | H. Sunagawa, H. Terada, A. Tsuchiya, K. Kobayashi, and H. Onodera | IPSJ Transactions on System LSI Design Methodology, vol.3, pp. 130-139, 2010/02 |
| Micro/nanoimprinting of Glass under High Temperature Using a CVD Diamond Mold | M. Komori, H. Uchiyama, H. Takebe, T. Kusuura, K. Kobayashi, K. Kuwahara, and T. Tsuchiya | Journal of Micromechanics and Microengineering, 065013, 2008/05 |
| A 90nm 48x48 LUT-Based FPGA Enhancing Speed and Yield Utilizing Within-Die Delay Variations | K. Kobayashi, K. Katsuki, M. Kotani, Y. Sugihara, Y. Kume, and H. Onodera | IEICE Trans. on Electronics, vol.E90-C, no. 10, pp. 1919-1926, 2007/10 |
| A 90 nm LUT Array for Speed and Yield Enhancement by Utilizing Within-Die Delay Variations | K. Katsuki, M. Kotani, K. Kobayashi, and H. Onodera | IEICE Trans. on Electronics, vol.E90-C, no. 4, pp. 699-707, 2007/04 |
| A Leakage Reduction Scheme for Sleep Transistors with Decoupling Capacitors in the Deep Submicron Era | K. Kobayashi, A. Higuchi, and H. Onodera | IEICE Trans. on Electronics, vol.E89-C, no. 6, pp. 838-843, 2006/06 |
| Alternative Self-Shielding for High-Speed and Reliable On-Chip Global Interconnect | Y. Yuyama, A. Tsuchiya, K. Kobayashi, and H. Onodera | IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol.E89-C, no. 3, pp. 327-333, 2006/03 |
| A resource-Shared VLIW Processor for Low-power On-Chip Multiprocessing in the Nanometer Era,pdf | K. Kobayashi, M. Aramoto, and H. Onodera | IEICE Trans. on Electronics, vol.E88-C, no. 4, pp. 552-558, 2005/04 |
| Instruction-Level Power Estimation Method by Considering Hamming Distance of Registers | A. Higuchi, K. Kobayashi, and H. Onodera | IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol.E87-A, no. 4, pp. 823-829, 2004/04 |
| An Efficient Motion Estimation Algorithm Using a Gyro Sensor | K. Kobayashi, R. Nakanishi, and H. Onodera | IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol.E87-A, no. 3, pp. 530-538, 2004/03 |
| A Comprehensive Simulation and Test Environment for Prototype VLSI Verification | K. Kobayashi, and H. Onodera | IEICE Trans. on Inf. & Syst., vol.E87-D, no. 3, pp. 630-636, 2004/03 |
| A Low-Power High-Performance Vector-Pipeline DSP for Low-Rate Videophones | K. Kobayashi, M. Eguchi, T. Iwahashi, T. Shibayama, S. Li, K. Takai, and H. Onodera | IEICE Trans. on Electronics, vol.E84-C, no. 2, pp. 193-201, 2001/02 |
| Physical Insights on Imprint and Application to Functional Memory with Ferroelectric Materials | Y. Fujii, D. Nagasawa, H. Nozawa, K. Kobayashi, and K. Tamaru | International Journal on Integrated Ferroelectrics, vol.33, no. 1-4, pp. 261-270, 2001/01 |
| Architecture and Performance Evaluation of a New Functional Memory: Functioal Memory for Addition | K. Kobayashi, M. Yamaoka, Y. Kobayashi, H. Onodera, and K. Tamaru | IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol.E83-A, no. 12, pp. 2400-2408, 2000/12 |
| A Real-Time Low-Rate Video Compression Algorithm Using Multi-Stage Hierarchical Vector Quantization | K. Kobayashi, K. Terada, H. Onodera, and K. Tamaru | IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol.E82-A, no. 2, pp. 215-222, 1999/02 |
| Memory Based Architecture and its Implementation Scheme Named Bit-Parallel Block-Parallel Functional Memory Type Parallel Processor BPBP FMPP | K. Tamaru, K. Kobayashi, and H. Onodera | Computers and Electrical Engineering, vol.24, pp. 17-31, 1998/06 |
| An LSI for Low Bit-Rate Image Compression Using Vector Quantization | K. Kobayashi, N. Nakamura, K. Terada, H. Onodera, and K. Tamaru | IEICE Trans. on Electronics, vol.Vol.E81-C, no. No.5, pp. 718-724, 1998/05 |
| A memory-based parallel processor for vector quantization: FMPP-VQ. | K. Kobayashi, M. Kinoshita, M. Takeuchi, H. Onodera, and K. Tamaru | IEICE Trans. on Electronics, vol.E80-C, no. 7, pp. 970--975, 1997/07 |
| A bit-parallel block-parallel functional memory type parallel processor architecture | K. Kobayashi, K. Tamaru, H. Yasuura, and H. Onodera | IEICE Trans. on Electronics, vol.E76-C, no. 7, pp. 1151-1158, 1993/07 |
| title | author | taken |
| Data Pattern Dependence of the Total Ionizing Dose Effect in 3D NAND Flash Memories,pdf | T. Ozawa, K. Kobayashi, and J. Furuta | Radiation Effects on Components and Systems, DW-24, 2024/09, Gran Canaria, Spain |
| IEEE International Conference on Quantum Computing and Engineering,pdf[URL] | T. Imagawa, R. Kishida, Y. Koyama, and K. Kobayashi | IEEE International Conference on Quantum Computing and Engineering, 2024/09, Montreal, Quebec, Canada |
| An Approach to Neutron-Induced SER Evaluation Using a Clinical 290 MeV/u Carbon Beam and Particle Transport Simulations,pdf[URL] | R. Nakajima, S. Sugitani, H. Sugisaki, T. Ito, J. Furuta, K. Kobayashi, and M. Sakai | IEEE International Reliability Physics Symposium, P43.RE, 2024/04, Dallas, TX, USA |
| A Partially-redundant Flip-flip Suitable for Mitigating Single Event Upsets in a FD-SOI Process with Low Performance Overhead,pdf[URL] | J. Furuta, S. Sugitani, R. Nakajima, and K. Kobayashi | IEEE International Reliability Physics Symposium, P41.RE, 2024/04, Dallas, TX, USA |
| Ring Oscillators with identical Circuit Structure to Measure Bias Temperature Instability,pdf[URL] | D. Kikuta, R. Kishida, and K. Kobayashi | International Conference on ASIC, 2023/10, Nanjing, China |
| Frequency Dependency of Soft Error Rates Based on Dynamic Soft Error Measurements,pdf[URL] | H. Sugisaki, R. Nakajima, S. Sugitani, J. Furuta, and K. Kobayashi | International Conference on IC Design and Technology, 2023/09, Tokyo, Japan |
| SEU Sensitivity of PMOS and NMOS Transistors in a 65 nm Bulk Process by α-Particle Irradiation,pdf[URL] | K. Yoshida, R. Nakajima, S. Sugitani, T. Ito, J. Furuta, and K. Kobayashi | International Conference on IC Design and Technology, pp. 72-75, 2023/09, Tokyo, Japan |
| Total Ionizing Dose Effect by Gamma-ray Irradiation and Recovery Phenomenon by Applying High Gate Bias to Commercial SiC Power MOSFETs,pdf[URL] | M. Mizushima, K. Kobayashi, and J. Furuta | International Conference on Solid State Devices and Materials, pp. 417-418, 2023/09, Nagoya, Japan |
| Radiation Hardness Evaluations of a Stacked Flip Flop in a 22nm FD-SOI Process by Heavy-Ion Irradiation,pdf[URL] | S. Sugitani, R. Nakajima, T. Ito, J. Furuta, K. Kobayashi, M. Louvat, F. Jacquet, J. Eloy, O. Montfort, J. Lionel, and V. Huard | IEEE International Symposium on On-Line Testing and Robust System Design, 2023/07, Platanias, Chania, Crete (Greece) |
| A 13-bit Radiation-Hardened SAR-ADC with Error Correction by Adaptive Topology Transformation,pdf[URL] | Y. Aoki, T. Iwata, T. Miki, K. Kobayashi, and T. Yoshikawa | IEEE International Reliability Physics Symposium, pp. 9B.3-1-9B.3-8, 2023/03, Monterey, CA, USA |
| Radiation Hardened Flip-Flops with low Area, Delay and Power Overheads in a 65 nm bulk process,pdf[URL] | S. Sugitani, R. Nakajima, K. Yoshida, J. Furuta, and K. Kobayashi | IEEE International Reliability Physics Symposium, pp. P54.RE-1-P54.RE-5, 2023/03, Monterey, CA, USA |
| Ultra Long-term Measurement Results of BTI-induced Aging Degradation on 7-nm Ring Oscillators,pdf[URL] | K. Kobayashi, T. Kishita, H. Nakano, J. Furuta, M. Igarashi, S. Kumashiro, M. Yabuuchi, and H. Sakamoto | IEEE International Reliability Physics Symposium, 7A.1, 2023/03, Monterey, CA, USA |
| Evaluation of Soft Error Tolerance on Flip-Flops Restoring from a Single Node Upset by C-elements ,pdf[URL] | T. Ito, R. Nakajima, J. Furuta, and K. Kobayashi | International Meeting for Future of Electron Devices, Kansai, R10, 2022/11, Kyoto, Japan |
| A Terrestrial SER Estimation Methodology with Simulation and Single-Source Irradiation Applicable to Diverse Neutron Sources[URL] | S. Abe, M. Hashimoto, W. Liao, T. Kato, H. Asai, K. Shimbo, H. Matsuyama, T. Sato, K. Kobayashi, and Y. Watanabe | Radiation Effects on Components and Systems, I3, 2022/10, Venice, Italy |
| Soft-error Tolerance by Guard-Gate Structures on Flip-Flops in 22/65 nm FD-SOI Technologies,pdf[URL] | R. Nakajima, T. Ito, T. Kii, M. Ebara, J. Furuta, K. Kobayashi, M. Louvat, F. Jacquet, O. Montfort, J. Lionel, and V. Huard | Radiation Effects on Components and Systems, G2, 2022/10, Venice, Italy |
| Single Bit Upsets versus Burst Errors of Stacked-Capacitor DRAMs Induced by High-Energy Neutron -SECDED is No Longer Effective-,pdf[URL] | M. Kamibayashi, K. Kobayashi, and M. Hashimoto | Radiation Effects on Components and Systems, DW8, 2022/10, Venice, Italy |
| Measurement of Total Ionizing Dose Effects on SiC Trench MOSFETs by Gamma-ray and Alpha-particle Irradiation,pdf[URL] | J. Furuta, M. Mizushima, and K. Kobayashi | Radiation Effects on Components and Systems, vol.D4, 2022/10, Venice, Italy |
| Radiation Hardened Flip-Flops Minimizing Area, Power, and Delay Overheads with 1/100 Lower Alpha-SER in a 130 nm Bulk Process,pdf[URL] | R. Nakajima, K. Ioki, J. Furuta, and K. Kobayashi | IEEE International Symposium on On-Line Testing and Robust System Design, 2022/09, Online |
| Nonvolatile Flip-Flops Using FiCC for IoT Processors with Intermittent Operations,pdf[URL] | Y. Abe, K. Kobayashi, and O. Hiroyuki | International Midwest Symposium on Circuits and Systems, 2022/08, online |
| Zero-standby-power Nonvolatile Standard Cell Memory Using FiCC for IoT Processors with Intermittent Operations,pdf[URL] | Y. Abe, K. Kobayashi, J. Shiomi, and O. Hiroyuki | Symposium on Low-Power and High-Speed Chips and Systems (COOL Chips), pp. 641-646, 2022/04, Tokyo, Japan |
| An Aging Degradation Suppression Scheme at Constant Performance by Controlling Supply Voltage and Body Bias in a 65 nm Fully-Depleted Silicon-On-Insulator Process,pdf[URL] | I. Suda, R. Kishida, and K. Kobayashi | IEEE International Reliability Physics Symposium, P4, 2022/03, Online |
| An Asynchronous Buck Converter by Using a Monolithic GaN IC Integrated by an Enhancement-Mode GaN-on-SOI Process,pdf[URL] | S. Noike, J. Nagao, J. Furuta, and K. Kobayashi | Workshop on Wide Bandgap Power Devices and Applications, pp. PO1_2, 2021/11, Online |
| A Capacitor-Based Multilevel Gate Driver for GaN HEMT Only with a Single Voltage Supply,pdf[URL] | T. Takahashi, J. Nagao, J. Furuta, and K. Kobayashi | Workshop on Wide Bandgap Power Devices and Applications, 2021/11, Online |
| Nonvolatile SRAM Using Fishbone-in-Cage Capacitor in a 180 nm Standard CMOS Process for Zero-standby and Instant-powerup Embedded Memory on IoT,pdf[URL] | T. Urabe, O. Hiroyuki, and K. Kobayashi | Symposium on Low-Power and High-Speed Chips and Systems (COOL Chips), 2021/04, Online |
| Bias Temperature Instability Depending on Body Bias through Buried Oxide (BOX) Layer in a 65 nm Fully-Depleted Silicon-On-Insulator Process,pdf[URL] | R. Kishida, I. Suda, and K. Kobayashi | IEEE International Reliability Physics Symposium, 4A.6, 2021/03, Online |
| Capacitor-Based Three-Level Gate Driver for GaN HEMT Only with a Single Voltage Supply,pdf[URL] | J. Nagao, J. Furuta, and K. Kobayashi | IEEE Workshop on Control and Modeling for Power Electronics, pp. 1-7, 2020/11, Online |
| Intrinsic Vulnerability to Soft Errors and Mitigation Technique by Layout Optimization on DICE Flip Flops in a 65 nm Bulk Process,pdf | F. Mori, M. Ebara, Y. Tsukita, J. Furuta, and K. Kobayashi | Radiation Effects on Components and Systems, PF-2, 2020/10, Online |
| A 1 MHz Boost DC-DC Converter with Turn on ZCS Capability to Reduce EMI,pdf[URL] | H. Yoshioka, J. Furuta, and K. Kobayashi | IEEE Workshop on Wide Bandgap Power Devices and Applications in Asia 2020, pp. 86-90, 2020/09, Online |
| Temperature Dependence of Bias Temperature Instability (BTI) in Long-term Measurement by BTI-sensitive and -insensitive Ring Oscillators Removing Environmental Fluctuation,pdf[URL] | T. Asuke, R. Kishida, J. Furuta, and K. Kobayashi | International Conference on ASIC, pp. B-8-5, 2019/11, Chongqing, China |
| Soft-Error Tolerance Depending on Supply Voltage by Heavy Ions on Radiation-Hardened Flip Flops in a 65 nm Bulk Process,pdf[URL] | Y. Tsukita, M. Ebara, J. Furuta, and K. Kobayashi | International Conference on ASIC, pp. A1-4, 2019/10, Chongqing, China |
| Soft Error Tolerance of Standard and Stacked Latches Dependending on Substrate Bias in a FDSOI Process Evaluated by Device Simulation,pdf[URL] | K. Kojima, J. Furuta, and K. Kobayashi | SOI-3D-Subthreshold Microelectronics Technology Unified Conference, 2019/10, San Jose, CA, USA |
| LVDS Transmitter for Cold-Spare Systems in High Flux Environments,pdf[URL] | T. Yoshikawa, A. Aoyama, T. Iwata, and K. Kobayashi | Radiation Effects on Components and Systems, 2019/09, Montpellier, France |
| Monolithically integrated GaN power ICs designed using the MVSG compact model for enhancement-mode p-GaN gate power HEMTs, logic transistors and resistors ,pdf[URL] | S. You, X. Li, D. Stefaan, G. Groeseneken, Z. Chen, J. Liu, Y. Yamashita, and K. Kobayashi | European Solid-State Device Electronics Conference, pp. 158-161, 2019/09, Krakow, Poland |
| Measuring SER by Neutron Irradiation between Volatile SRAM-based and Nonvolatile Flash-based FPGAs,pdf[URL] | Y. Kawano, Y. Tsukita, J. Furuta, and K. Kobayashi | Radiation Effects on Components and Systems, DW-24, 2019/09, Montpellier, France |
| Evaluation of Soft-Error Tolerance by Neutrons and Heavy Ions on Flip Flops with Guard Gates in a 65 nm Thin BOX FDSOI Process,pdf | M. Ebara, K. Yamada, K. Kojima, Y. Tsukita, J. Furuta, and K. Kobayashi | Radiation Effects on Components and Systems, F-1, 2019/09, Montpellier, France |
| A Robust Simulation Method for Breakdown with Voltage Boundary Condition Utilizing Negative Time Constant Information,pdf[URL] | S. Kumashiro, T. Kamei, A. Hiroki, and K. Kobayashi | IEEE International Conference on Simulation of Semiconductor Processes and Devices , pp. 33-36, 2019/09, Udine, Italy |
| Compact Modeling of NBTI Replicating AC Stress / Recovery from a Single-shot Long-term DC Measurement,pdf[URL] | T. Hosaka, S. Nishizawa, R. Kishida, T. Matsumoto, and K. Kobayashi | IEEE International Symposium on On-Line Testing and Robust System Design, pp. 305-309, 2019/07, Rhodos, Greece |
| Total Ionizing Dose Effects by Alpha Irradiation on Circuit Performance and SEU Tolerance in thin BOX FDSOI Process,pdf[URL] | T. Yoshida, K. Kobayashi, and J. Furuta | IEEE International Symposium on On-Line Testing and Robust System Design, pp. 236-238, 2019/07, Rhodos, Greece |
| Comparison of Radiation Hardness of Stacked Transmission-Gate Flip Flop and Stacked Tristate-Inverter Flip Flop in a 65 nm Thin BOX FDSOI Process,pdf[URL] | M. Ebara, K. Yamada, J. Furuta, and K. Kobayashi | IEEE International Symposium on On-Line Testing and Robust System Design, pp. 1-6, 2019/07 |
| Monolithically Integrated Gate Driver for MHz Switching with an External Inductor,pdf[URL] | J. Nagao, Y. Yamashita, J. Furuta, K. Kobayashi, S. Stoffels, P. Niels, and D. Stefaan | IEEE Workshop on Control and Modeling for Power Electronics, pp. PS1.19, 2019/06, Toronto, ON, Canada |
| An Accurate Device-Level Simulation Method to Estimate Cross Sections of Single Event Upsets by Silicon Thickness in Raised Layer,pdf[URL] | K. Kojima, K. Yamada, J. Furuta, and K. Kobayashi | IEEE International Reliability Physics Symposium, pp. P.SE.4.1-P.SE.4.5, 2019/04, Monterey, CA, USA |
| Impact of Combinational Logic Delay for Single Event Upset on Flip Flops in a 65 nm FDSOI Process,pdf[URL] | J. Furuta, Y. Tsukita, K. Yamada, M. Ebara, K. Kojima, and K. Kobayashi | IEEE International Reliability Physics Symposium, pp. P.SE.3.1-P.SE.3.4, 2019/04, Monterey, CA, USA |
| Extracting BTI-induced Degradation without Temporal Factors by Using BTI-Sensitive and BTI-Insensitive Ring Oscillators,pdf[URL] | R. Kishida, T. Asuke, J. Furuta, and K. Kobayashi | International Conference on Microelectronic Test Structure, pp. 24-27, 2019/03, Fukuoka, Japan |
| Monolithically Integrated E-Mode GaN-on-SOI Gate Driver with Power GaN-HEMT for MHz-Switching,pdf[URL] | Y. Yamashita, S. Stoffels, P. Niels, D. Stefaan, and K. Kobayashi | Workshop on Wide Bandgap Power Devices and Applications, pp. 231-236, 2018/11, Atlanta, GA, USA |
| Radiation-Hardened Flip-Flops with Small Area and Delay Overheads Using Guard-Gates in FDSOI Processes,pdf[URL] | K. Yamada, J. Furuta, and K. Kobayashi | SOI-3D-Subthreshold Microelectronics Technology Unified Conference, 2018/10, Burlingame, CA, USA |
| Threshold Dependence of Soft-Errors induced by alpha particles and Heavy Ions on Flip Flops in a 65 nm Thin BOX FDSOI,pdf[URL] | M. Ebara, K. Yamada, K. Kojima, J. Furuta, and K. Kobayashi | SOI-3D-Subthreshold Microelectronics Technology Unified Conference, 2018/10, Burlingame, CA, USA |
| Evaluation of Heavy-Ion-Induced SEU Cross Sections of a 65 nm Thin BOX FD-SOI Flip-Flops Based on Stacked Inverter,pdf[URL] | J. Furuta, K. Kojima, and K. Kobayashi | Radiation Effects on Components and Systems, 2018/09, Goeteborg, Sweden |
| Radiation-Hardened Structure to Reduce Sensitive Range of a Stacked Structure for FDSOI,pdf[URL] | K. Yamada, M. Ebara, K. Kojima, Y. Tsukita, J. Furuta, and K. Kobayashi | Radiation Effects on Components and Systems, 2018/09, Goeteborg, Sweden |
| Sensitivity to Soft Errors of NMOS and PMOS Transistors Evaluated by Latches with Stacking Structures in a 65 nm FDSOI Process,pdf[URL] | K. Yamada, H. Maruoka, J. Furuta, and K. Kobayashi | IEEE International Reliability Physics Symposium, pp. P-SE.3-1-5, 2018/03, Barlingame, CA, USA |
| Design of gate driver monolithically integrated with power p-GaN HEMT based on E-mode GaN-on-Si technology,pdf[URL] | Y. Yamashita, S. Stoffels, P. Niels, D. Stefaan, and K. Kobayashi | Texas Power and Energy Conference, 2018/02, Houston, TX, USA |
| Radiation-Hardened Flip-Flops with Low Delay Overheads Using PMOS Pass-Transistors to Suppress a SET Pulse in a 65 nm FDSOI Process,pdf[URL] | K. Yamada, H. Maruoka, J. Furuta, and K. Kobayashi | Radiation Effects on Components and Systems, 2017/10, Geneva, Switzerland |
| Plasma Induced Damage Depending on Antenna Layers in Ring Oscillators,pdf[URL] | R. Kishida, J. Furuta, and K. Kobayashi | International Conference on Solid State Devices and Materials, pp. 209-210, 2017/09, Sendai, Japan |
| MHz-Switching-Speed Current-Source Gate Driver for SiC Power MOSFETs,pdf[URL] | S. Inamori, J. Furuta, and K. Kobayashi | European Conference on Power Electronics and Applications, pp. DS1a.2.1-2.7, 2017/09, Warsaw, Poland |
| Analysis of Neutron-induced Soft Error Rates on 28nm FD-SOI and 22nm FinFET Latches by the PHITS-TCAD Simulation System,pdf[URL] | J. Furuta, S. Umehara, and K. Kobayashi | IEEE International Conference on Simulation of Semiconductor Processes and Devices , pp. 185-188, 2017/09, Kamakura, Japan |
| An Accurate Metric to Control Time Step of Transient Device Simulation by Matrix Exponential Method,pdf[URL] | S. Kumashiro, T. Kamei, A. Hiroki, and K. Kobayashi | IEEE International Conference on Simulation of Semiconductor Processes and Devices , pp. 37-40, 2017/09, Kamakura, Japan |
| Design of RCD Snubber Considering Wiring Inductance for MHz-Switching of SiC-MOSFET,pdf[URL] | Y. Yamashita, J. Furuta, S. Inamori, and K. Kobayashi | IEEE Workshop on Control and Modeling for Power Electronics, O10-2, 2017/07, Stanford, CA, USA |
| Circuit-level Simulation Methodology for Random Telegraph Noise by Using Verilog-AMS,pdf[URL] | T. Komawaki, M. Yabuuchi, R. Kishida, J. Furuta, T. Matsumoto, and K. Kobayashi | International Conference on IC Design and Technology, I2, pp. I2.01-04, 2017/05, Austin, TX, USA |
| A Flip-Flop with High Soft-error Tolerance and Small Power and Delay Overheads,pdf[URL] | K. Yamada, H. Maruoka, J. Furuta, and K. Kobayashi | Symposium on Low-Power and High-Speed Chips and Systems (COOL Chips), poster-1, 2017/04, Yokohama, Japan |
| A 16 nm FinFET Radiation-hardened Flip-Flop, Bistable Cross-coupled Dual-Modular-Redundancy FF for Terrestrial and Outer-Space Highly-reliable Systems,pdf[URL] | K. Kobayashi, J. Furuta, H. Maruoka, M. Hifumi, S. Kumashiro, T. Kato, and S. Kohri | IEEE International Reliability Physics Symposium, pp. SE2.1-SE2.3, 2017/04, Monterey, CA, USA |
| Influence of Layout Structures to Soft Errors Caused by Higher-energy Particles on 28/65 nm FDSOI Flip-Flops,pdf[URL] | M. Hifumi, H. Maruoka, S. Umehara, K. Yamada, J. Furuta, and K. Kobayashi | IEEE International Reliability Physics Symposium, pp. SE5.1-SE5.4, 2017/04, Monterey, CA, USA |
| Circuit Analysis and Defect Characteristics Estimation Methods Using Bimodal Defect-Centric Random Telegraph Noise Model,pdf[URL] | M. Yabuuchi, A. Oshima, T. Komawaki, R. Kishida, J. Furuta, K. Kobayashi, P. Weckx, B. Kaczer, T. Matsumoto, and H. Onodera | International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, pp. 47-52, 2017/03, Monterey, CA, USA |
| Degradation Caused by Negative Bias Temperature Instability Depending on Body Bias on NMOS or PMOS in 65 nm Bulk and Thin-BOX FDSOI Processes,pdf[URL] | R. Kishida, and K. Kobayashi | Electron Devices Technology and Manufacturing, pp. 122-123, 2017/03, Toyama, Japan |
| The Impact of RTN-Induced Temporal Performance Fluctuation Against Static Performance Variation,pdf | T. Matsumoto, K. Kobayashi, and H. Onodera | Electron Devices Technology and Manufacturing, pp. 31-32, 2017/03 |
| A Low Surge Voltage and Fast Speed Gate Driver for SiC MOSFET with Switched Capacitor Circuit,pdf[URL] | M. Fei, J. Furuta, and K. Kobayashi | Workshop on Wide Bandgap Power Devices and Applications, pp. 282-285, 2016/11, Fayetteville, AR, USA |
| Correlations between Plasma Induced Damage and Negative Bias Temperature Instability in 65 nm Bulk and Thin-BOX FDSOI Processes,pdf | R. Kishida, and K. Kobayashi | SOI-3D-Subthreshold Microelectronics Technology Unified Conference, pp. 25-27, 2016/10, Burlingame, CA, USA |
| A Radiation-hard Layout Structure to Control Back-Gate Biases in a 65 nm Thin-BOX FDSOI Process,pdf | J. Yamaguchi, J. Furuta, and K. Kobayashi | SOI-3D-Subthreshold Microelectronics Technology Unified Conference, pp. 28-30, 2016/10, Burlingame, CA, USA |
| Negative Bias Temperature Instability by Body Bias on Ring Oscillators in Thin BOX Fully-Depleted Silicon on Insulator Process,pdf[URL] | R. Kishida, and K. Kobayashi | International Conference on Solid State Devices and Materials, pp. 711-712, 2016/09, Tsukuba, Japan |
| A Non-Redundant Low-Power Flip Flop with Stacked Transistors in a 65 nm Thin BOX FDSOI Process,pdf[URL] | H. Maruoka, M. Hifumi, J. Furuta, and K. Kobayashi | Radiation Effects on Components and Systems, 2016/09, Bremen, Germany |
| Physical-Based RTN Modeling of Ring Oscillators in 40-nm SiON and 28-nm HKMG by Bimodal Defect-Centric Behaviors,pdf[URL] | A. Oshima, T. Komawaki, K. Kobayashi, R. Kishida, P. Weckx, B. Kaczer, T. Matsumoto, and H. Onodera | IEEE International Conference on Simulation of Semiconductor Processes and Devices , pp. 327-330, 2016/09, Nurnberg, Germany |
| Soft Error Tolerance of Redundant Flip-Flops by Heavy-Ion Beam Tests in 65 nm bulk and FDSOI Processes | E. Sonezaki, M. Hifumi, J. Furuta, and K. Kobayashi | IEEE Nuclear and Space Radiation Effects Conference, 2016/07, Portland, OR, USA |
| Correlations between Radiation Hardness and Variation of FFs Depending on Layout Structures in a 28 nm Thin BOX FD-SOI Process by Alpha Particle Irradiation,pdf | H. Maruoka, M. Hifumi, S. Kanda, J. Furuta, and K. Kobayashi | Silicon Errors in Logic - System Effects, 2016/03, Austion, TX, USA |
| Analysis of Terrestrial Single Event Upsets by Body Biases in a 28 nm UTBB Process by a PHITS-TCAD Simulation System,pdf | S. Umehara, K. Zhang, S. Kanda, M. Hifumi, J. Furuta, and K. Kobayashi | International Workshop on Radiation Effects on Semiconductor Devices for Space Applications, pp. 53-56, 2015/11, Kiryu, Gunma, Japan |
| Radiation Hardness Evaluations of FFs on 28nm and 65nm Thin BOX FD-SOI Processes by Heavy-Ion Irradiation,pdf | M. Hifumi, E. Sonezaki, J. Furuta, and K. Kobayashi | International Workshop on Radiation Effects on Semiconductor Devices for Space Applications, pp. 93-96, 2015/11, Kiryu, Gunma, Japan |
| Estimation of Soft Error Tolerance according to the Thickness of Buried Oxide and Body Bias 28-nm and 65-nm in FD-SOI Processes by a Monte-Carlo Simulation,pdf | K. Zhang, J. Yamaguchi, S. Kanda, J. Furuta, and K. Kobayashi | International Conference on Solid State Devices and Materials, pp. 1026-1027, 2015/09, Sapporo, Hokkaido, Japan |
| Analysis of BOX Layer Thickness on SERs of 65 and 28nm FD-SOI Processes by a Monte-Carlo Based Simulation Tool,pdf[URL] | K. Zhang, S. Kanda, J. Yamaguchi, J. Furuta, and K. Kobayashi | Radiation Effects on Components and Systems, 2015/09, Moscow, Russia |
| A Radiation-Hardened Non-redundant Flip-Flop, Stacked Leveling Critical Charge Flip-Flop in a 65 nm Thin BOX FD-SOI Process,pdf[URL] | J. Yamaguchi, J. Furuta, and K. Kobayashi | Radiation Effects on Components and Systems, 2015/09, Moscow, Russia |
| Analysis of the Soft Error Rates on 65-nm SOTB and 28-nm UTBB FD-SOI Structures by a PHITS- TCAD Based Simulation Tool,pdf[URL] | K. Zhang, S. Kanda, J. Yamaguchi, J. Furuta, and K. Kobayashi | IEEE International Conference on Simulation of Semiconductor Processes and Devices , 2015/09, Washington DC, USA |
| Impact of Random Telegraph Noise on Ring Oscillators Evaluated by Circuit-level Simulations,pdf[URL] | A. Oshima, P. Weckx, B. Kaczer, K. Kobayashi, and T. Matsumoto | International Conference on IC Design and Technology, 2015/06, Leuven, Bergium |
| Negative Bias Temperature Instability Caused by Plasma Induced Damage in 65 nm Bulk and Silicon On Thin BOX (SOTB) Processes,pdf[URL] | R. Kishida, A. Oshima, and K. Kobayashi | IEEE International Reliability Physics Symposium, pp. CA.2.1-CA.2.5, 2015/04, Monterey, CA, USA |
| Analysis of Soft Error Rates by Supply Voltage in 65-nm SOTB and 28-nm UTBB Structures by a PHITS-TCAD Simulation System,,pdf[URL] | K. Zhang, S. Kanda, J. Yamaguchi, J. Furuta, and K. Kobayashi | Silicon Errors in Logic - System Effects, 2015/03, Austin, TX, USA |
| Analysis of the Distance Dependent Multiple Cell Upset Rates on 65-nm Redundant Latches by a PHITS-TCAD Simulation System,pdf | K. Zhang, J. Furuta, and K. Kobayashi | Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 89-93, 2015/03, Jiaosi, Yilan, Taiwan |
| Reliability-Configurable Mixed-Grained Reconfigurable Array Compatible with High-Level Synthesis,pdf[URL] | M. Hashimoto, D. Dawood, H. Kounoura, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, O. Hiroyuki, T. Imagawa, K. Wakabayashi, T. Onoye, and H. Onodera | Asia and South Pacific Design Automation Conference, pp. 14 - 15, 2015/01, Chiba, Japan |
| Initial Frequency Degradation and Variation on Ring Oscillators from Plasma Induced Damage in Fully-Depleted Silicon on Insulator Process,pdf[URL] | R. Kishida, A. Oshima, M. Yabuuchi, and K. Kobayashi | IEEE/ACM Workshop on Variability Modeling and Characterization, 2014/11, San Jose, CA, USA |
| Initial and Long-Term Frequency Degradation on Ring Oscillators from Plasma Induced Damage in 65 nm Bulk and Silicon On Thin BOX processes,pdf[URL] | R. Kishida, A. Oshima, M. Yabuuchi, and K. Kobayashi | International Conference on Solid State Devices and Materials, pp. 52-53, 2014/09, Tsukuba, Japan |
| Radiation Hardness Evaluations of 65 nm FD-SOI and Bulk processes by Measuring SET Pulse Widths and SEU Rates,pdf[URL] | E. Sonezaki, J. Furuta, and K. Kobayashi | International Conference on Solid State Devices and Materials, pp. 840-841, 2014/09, Tsukuba, Japan |
| Correlation between BTI-Induced Degradations and Process Variations by Measuring Frequency of ROs ,pdf[URL] | M. Yabuuchi, R. Kishida, and K. Kobayashi | International Meeting for Future of Electron Devices, Kansai, pp. 128-131, 2014/06, Kyoto, Japan |
| Impact of Body Bias on Soft Error Tolerance of Bulk and Silicon on Thin BOX Structure in 65-nm Process,pdf | K. Zhang, Y. Manzawa, and K. Kobayashi | IEEE International Reliability Physics Symposium, pp. SE2.1-SE2.4, 2014/06, Waicoloa, HI, USA |
| A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14μA Sleep Current using Reverse Body Bias Assisted 65nm SOTB CMOS Technology,pdf[URL] | K. Ishibashi, N. Sugii, K. Usami, A. Hideharu, K. Kobayashi, P. Cong-Kha, H. Makiyama, Y. Yoshiki , H. Shinohara, T. Iwamatsu, Y. Yamaguchi, H. Oda, T. Hasegawa, S. Okanishi, H. Yanagita, S. Kamohara, M. Kadoshima, K. Maekawa, T. Yamashita, D. Le, T. Yomogita, M. Kudo, K. Kitamori, S. Kondo, and Y. Manzawa | Symposium on Low-Power and High-Speed Chips and Systems (COOL Chips), pp. 1-3, 2014/04, Yokohama, Japan |
| Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing,pdf | D. Dawood, H. Kounoura, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, Y. Mitsuyama, T. Imagawa, S. Noda, K. Wakabayashi, M. Hashimoto, T. Onoye, and H. Onodera | IEEE Asian Solid-State Circuits Conference, pp. 313-316, 2013/11, Singapore |
| Radiation-Hard Layout Structures on Bulk and SOI Process by Device-Level Simulations,pdf | K. Zhang, and K. Kobayashi | Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 275-279, 2013/10, Sapporo, Japan |
| Impact of Drive Strength and Well-Contact Density on Heavy-Ion-Induced Single Event Transient,pdf | J. Furuta, M. Masuda, K. Takeuchi, K. Kobayashi, and H. Onodera | Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 165-169, 2013/10, Sapporo, Japan |
| Dependence of Cell Distance and Well-contact Density of MCU Rates by Device Simulations and Neutron Experiments in a 65-nm Bulk Process,pdf | K. Zhang, J. Furuta, K. Kobayashi, and H. Onodera | Radiation Effects on Components and Systems, 2013/09, Oxford, UK |
| A Low-Power and Area-Efficient Radiation-Hard Redundant Flip-Flop, DICE ACFF, in a 65 nm Thin-BOX FD-SOI,pdf[URL] | K. Kubota, M. Masuda, J. Furuta, Y. Manzawa, S. Kanda, K. Kobayashi, and H. Onodera | Radiation Effects on Components and Systems, PC-2, 2013/09, Oxford, UK |
| Impact of Cell Distance and Well-contact Density on Neutron-induced Multiple Cell Upsets,pdf | J. Furuta, K. Kobayashi, and H. Onodera | IEEE International Reliability Physics Symposium, pp. 6C.3.1-6C.3.4, 2013/04, Monterey, CA, USA |
| Contributions of Charge Sharing and Bipolar Effects to Cause or Suppress MCUs on Redundant Latches,pdf | K. Zhang, and K. Kobayashi | IEEE International Reliability Physics Symposium, pp. SE.5.1-SE.5.4, 2013/04, Monterey, CA, USA |
| Impact of Random Telegraph Noise on CMOS Logic Delay Uncertainty,pdf | T. Matsumoto, K. Kobayashi, and H. Onodera | International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, 2013/03, Lake Tahoe, NV, USA |
| A Low-Power and Area-Efficient Radiation-Hard Redundant Flip-Flop: DICE ACFF ,pdf[URL] | K. Kubota, M. Masuda, and K. Kobayashi | Silicon Errors in Logic - System Effects, 2013/03 |
| Impact of Cell Distance and Well Contact Density on Neutron-Induced Multiple Cell Upsets,pdf[URL] | J. Furuta, K. Kobayashi, and H. Onodera | Silicon Errors in Logic - System Effects, 2013/03, Stanford, CA, USA |
| Measurement Results of Substrate Bias Dependency on Negative Bias Temperature Instability Degradation in a 65 nm Process,pdf[URL] | S. Tanihiro, M. Yabuuchi, and K. Kobayashi | Components, Packaging, and Manufacturing Technology Symposium Japan, pp. 289-292, 2012/12, Kyoto, Japan |
| Impact of Random Telegraph Noise on CMOS Logic Delay Uncertainty under Low Voltage Operation,pdf | T. Matsumoto, K. Kobayashi, and H. Onodera | International Electron Device Meeting, pp. 25.6.1-25.6.4, 2012/12, San Francisco, CA, USA |
| Measurement of Distance-dependent Multiple Upsets of Flip-Flops in 65nm CMOS Process,pdf[URL] | J. Furuta, K. Kobayashi, and H. Onodera | International Workshop on Radiation Effects on Semiconductor Devices for Space Applications, pp. 154-156, 2012/12, Tsukuba, Japan |
| Impact of Body-Biasing Technique on RTN-induced CMOS Logic Delay Uncertainty,pdf | T. Matsumoto, K. Kobayashi, and H. Onodera | IEEE/ACM Workshop on Variability Modeling and Characterization, 2012/11, San Jose, CA, USA |
| A 65 nm Low-Power Adaptive-Coupling Redundant Flip- Flops,pdf | M. Masuda, K. Kubota, R. Yamamoto, J. Furuta, K. Kobayashi, and H. Onodera | Radiation Effects on Components and Systems, pp. I-1.1-5, 2012/09, Biarritz, France |
| Impact of Body-Biasing Technique on RTN-induced Delay Fluctuation,pdf | T. Matsumoto, K. Kobayashi, and H. Onodera | International Conference on Solid State Devices and Materials, pp. 1130-1131, 2012/09, Kyoto, Japan |
| Impact on Delay due to Random Telegraph Noise Under Low Voltage Operation in Logic Circuits,pdf | S. Nishimura, T. Matsumoto, K. Kobayashi, and H. Onodera | International Conference on Solid State Devices and Materials, pp. 170-171, 2012/09, Kyoto, Japan |
| Effects of Neutron-Induced Well Potential Perturbation for Multiple Cell Upset of Flip-Flops in 65 nm | J. Furuta, R. Yamamoto, K. Kobayashi, and H. Onodera | IEEE Nuclear and Space Radiation Effects Conference, 2012/07, Miami, FL, USA |
| DARA: A Low-Cost Reliable Architecture Based on Unhardened Devices and its Case Study of Radiation Stress Test | J. Yao, Y. Nakashima, S. Okada, and K. Kobayashi | IEEE Nuclear and Space Radiation Effects Conference, 2012/07, Miami, FL, USA |
| Circuit Characteristic Analysis Considering NBTI and PBTI-Induced Delay Degradation,pdf | M. Yabuuchi, and K. Kobayashi | International Meeting for Future of Electron Devices, Kansai, pp. 70-71, 2012/05, Osaka, Japan |
| Structure Dependence of Reduced Saturation Current Influenced by Source and Drain Resistances for 17 nm MOSFETs,pdf | J. Yoon, A. Hiroki, and K. Kobayashi | International Meeting for Future of Electron Devices, Kansai, pp. 92-93, 2012/05, Osaka, Japan |
| Parasitic Bipolar Effects on Soft Errors to Prevent Simultaneous Flips of Redundant Flip-Flops,pdf | K. Zhang, R. Yamamoto, J. Furuta, K. Kobayashi, and H. Onodera | IEEE International Reliability Physics Symposium, pp. 5B.2.1-5B.2.4, 2012/04, Anaheim, CA, USA |
| Evaluation of Parasitic Bipolar Effects on Neutron- Induced SET Rates for Logic Gates,pdf | J. Furuta, R. Yamamoto, K. Kobayashi, and H. Onodera | IEEE International Reliability Physics Symposium, pp. SE.5.1-SE5.5, 2012/04, Anaheim, CA, USA |
| Device-level Simulations of Parasitic Bipolar Mechanism on Preventing MCUs of Redundant Filp-Flops,pdf | K. Zhang, R. Yamamoto, and K. Kobayashi | Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 330 - 333, 2012/03, Beppu, Japan |
| Degradation of Oscillation Frequency of Ring Oscillators Placed on a 90 nm FPGA,pdf | S. Ishii, and K. Kobayashi | Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 217 - 221, 2012/03, Beppu, Japan |
| Correlations between Well Potential and SEUs Measured by Well-Potential Perturbation Detectors in 65nm,pdf | J. Furuta, R. Yamamoto, K. Kobayashi, and H. Onodera | IEEE Asian Solid-State Circuits Conference, pp. 209-212, 2011/11, Jeju, Korea |
| Impact of RTN and NBTI on Synchronous Circuit Reliability,pdf | T. Matsumoto, K. Kobayashi, and H. Onodera | IEEE/ACM Workshop on Variability Modeling and Characterization, 2011/11, San Jose, CA, USA |
| Multi-core LSI Lifetime Extension by NBTI-Recovery-based Self-healing,pdf | T. Matsumoto, H. Makino, K. Kobayashi, and H. Onodera | International Conference on Solid State Devices and Materials, G-3-1, pp. 1045-1046, 2011/09, Nagoya, Japan |
| An Area-efficient 65 nm Radiation-Hard Dual-Modular Flip-Flop to Avoid Multiple Cell Upsets | R. Yamamoto, C. Hamanaka, J. Furuta, K. Kobayashi, and H. Onodera | IEEE Nuclear and Space Radiation Effects Conference, 2011/07, Las Vegas, NV, USA |
| An estimation of saturation current influenced by source and drain resistances for sub-20nm MOSFETs ,pdf[URL] | J. Yoon, A. Hiroki, T. Sano, and K. Kobayashi | International Meeting for Future of Electron Devices, Kansai, pp. 56-57, 2011/05, Osaka, Japan |
| The Impact of RTN on Performance Fluctuation in CMOS Logic Circuits,pdf[URL] | K. Ito, T. Matsumoto, S. Nishizawa, H. Sunagawa, K. Kobayashi, and H. Onodera | IEEE International Reliability Physics Symposium, pp. CR.5.1-CR.5.4, 2011/04, Monterey, CA, USA |
| Measurement of Neutron-induced SET Pulse Width Using Propagation-induced Pulse Shrinking,pdf[URL] | J. Furuta, C. Hamanaka, K. Kobayashi, and H. Onodera | IEEE International Reliability Physics Symposium, pp. 5B.2.1-5B.2.5, 2011/04, Monterey, CA, USA |
| Variation-sensitive Monitor Circuits for Estimation of Die-to-Die Process Variation,pdf[URL] | I. A.K.M Mahfuzul, A. Tsuchiya, K. Kobayashi, and H. Onodera | International Conference on Microelectronic Test Structure, pp. 153-157, 2011/04, Amsterdam, Germany |
| Modeling of Random Telegraph Noise under Circuit Operation - Simulation and Measurement of RTN-induced delay fluctuation,pdf[URL] | K. Ito, T. Matsumoto, S. Nishizawa, H. Sunagawa, K. Kobayashi, and H. Onodera | International Symposium on Quality Electronic Design, pp. 22-27, 2011/03, Santa Clala, CA, USA |
| A 65nm Flip-Flop Array to Measure Soft Error Resiliency against High-Energy Neutron and Alpha Particles,pdf[URL] | J. Furuta, C. Hamanaka, K. Kobayashi, and H. Onodera | Asia and South Pacific Design Automation Conference, pp. 83-84, 2011/01, Yokohama, Japan |
| Minimal Roll-Back Based Recovery Scheme for Fault Toleration in Pipeline Processors,pdf[URL] | J. Yao, R. Watanabe, T. Nakada, H. Shimada, Y. Nakashima, and K. Kobayashi | Pacific Rim International Symposium on Dependable Computing, pp. 237-238, 2010/12, Tokyo, Japan |
| Evaluation of FPGA design guardband caused by inhomogeneous NBTI degradation considering process variations,pdf[URL] | M. Yabuuchi, and K. Kobayashi | International Conference on Field Programmable Technologies, pp. 417-420, 2010/12, Beijing, China |
| Circuit Performance Degradation on FPGAs Considering NBTI and Process Variations,pdf | M. Yabuuchi, and K. Kobayashi | Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 126-129, 2010/10, Taipei, Taiwan |
| A 65nm CMOS 400ns Measurement Delay NBTI-Recovery Sensor by Minimum Assist Circuit,pdf | T. Matsumoto, H. Makino, K. Kobayashi, and H. Onodera | International Conference on Solid State Devices and Materials, G-3-4, 2010/09, Tokyo, Japan |
| A 65nm Bistable Cross-coupled Dual Modular Redundancy Flip-Flop Capable of Protecting Soft Errors on the C-element,pdf[URL] | J. Furuta, C. Hamanaka, K. Kobayashi, and H. Onodera | VLSI Circuit Symposium, pp. 123-124, 2010/06, Honolulu, Hawaii, USA |
| Variability Characterization Using an RO-array Test Structure,pdf | S. Nishizawa, K. Kobayashi, and H. Onodera | IEEE International Workshop on Design for Manufacturability & Yield, pp. 7-10, 2010/06, Anaheim, CA, USA |
| Implementation and Evaluation of a Superscalar Processor Based on Dynamic Adaptive Redundant Architecture,pdf | R. Watanabe, J. Yao, H. Shimada, and K. Kobayashi | Symposium on Low-Power and High-Speed Chips and Systems (COOL Chips), pp. 195, 2010/04, Yokohama, Japan |
| Measurement Results of Multiple Cell Upsets on a 65nm Tapless Flip-Flop Array,pdf | J. Furuta, K. Kobayashi, and H. Onodera | Silicon Errors in Logic - System Effects, 2010/03, Stanford, USA |
| Process-sensitive Monitor Circuits for Estimation of Die-to-Die Process Variability,pdf | I. A.K.M Mahfuzul, A. Tsuchiya, K. Kobayashi, and H. Onodera | International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, 2010/03, San Francisco, CA, USA |
| A Stage-Level Recovery Scheme in Scalable Pipeline Modules for High Dependability,pdf[URL] | J. Yao, H. Shimada, and K. Kobayashi | International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems, vol.1, pp. 21-19, 2009/05, Maui, HI, USA |
| Effect of Regularity-Enhanced Layout on Printability and Circuit Performance of Standard Cells ,pdf | H. Sunagawa, H. Terada, A. Tsuchiya, K. Kobayashi, and H. Onodera | International Symposium on Quality Electronic Design, pp. 195-200, 2009/03 |
| A Stage-Level Recovery Scheme in Scalable Pipeline Modules for High Dependability | J. Yao, H. Shimada, and K. Kobayashi | International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems, 2009/03 |
| Embedded Delay Detectors to Choose the Fastest Route in FPGAs for Variation-aware Reconfiguration | Y. Kume, Y. Sugihara, N. Lai Cam, K. Kobayashi, and H. Onodera | Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 81, 2009/03 |
| Soft-error Resiliency Evaluation on Delayed Multiple-modular Flip-Flops | J. Furuta, Y. Moritani, K. Kobayashi, and H. Onodera | Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 352-357, 2009/03 |
| A Ring-Oscillator Array Circuit for Measurement and Modeling of Gate Delay Variability | H. Terada, A. Tsuchiya, and K. Kobayashi | Workshop on Test Structure Design for Variability Characterization, 2008/11 |
| A Variation-aware Constant-Order Optimization Scheme Utilizing Delay Detectors to Search for Fastest Paths on FPGAs | K. Kobayashi, Y. Kume, N. Lai Cam, Y. Sugihara, and H. Onodera | International Conference on Field Programmable Logic and Applications, pp. 107-112, 2008/09 |
| Performance Optimization by Track Swapping on Critical Paths Utilizing Random Variations for FPGAs | Y. Sugihara, Y. Kume, K. Kobayashi, and H. Onodera | International Conference on Field Programmable Logic and Applications, pp. 503-506, 2008/09 |
| Speed and Yield Enhancement by Track Swapping on Critical Paths Utilizing Random Variations for FPGAs | Y. Sugihara, Y. Kume, K. Kobayashi, and H. Onodera | International Symposium on Field-Programmable Gate Arrays , pp. 257-258, 2008/02 |
| Estimation of Yield Enhancement by Critical Path Reconfiguration Utilizing Random Variations on Deep-submicron FPGAs | Y. Sugihara, Y. Kume, K. Kobayashi, and H. Onodera | Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 183, 2007/10 |
| A 90nm 8x16 FPGA Enhancing Speed and Yield Utilizing Within-Die Variations | Y. Sugihara, M. Kotani, K. Katsuki, K. Kobayashi, and H. Onodera | Asia and South Pacific Design Automation Conference, pp. 122-123, 2007/01 |
| A 90nm 8x16 LUT-based FPGA Enhancing Speed and Yield Utilizing Within-Die Variations | M. Kotani, K. Katsuki, K. Kobayashi, and H. Onodera | European Solid-State Circuits Conference, pp. 110-113, 2006/09 |
| A Yield and Speed Enhancement Technique Using Reconfigurable Devices against Within-Die Variations on the Nanometer Regime | K. Kobayashi, M. Kotani, K. Katsuki, Y. Takatsukasa, Y. Ogata, Y. Sugihara, and H. Onodera | International Conference on Field Programmable Logic and Applications, pp. 761-764, 2006/08 |
| Extracting a Random Component of Variation from Measurement Results of a 90 nm LUT Array | K. Katsuki, M. Kotani, K. Kobayashi, and H. Onodera | Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 197-200, 2006/04 |
| Deterministic/Probablistic Noise and Bit Error Rate Modeling on On-chip Global Interconnect | Y. Yuyama, K. Kobayashi, and H. Onodera | Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 214-218, 2006/04 |
| Measurement Results of Within-Die Variability on a 90nm LUT Array for Speed and Yield Enhancement of Reconfigurable Devices | K. Katsuki, M. Kotani, K. Kobayashi, and H. Onodera | Asia and South Pacific Design Automation Conference, pp. 110-111, 2006/01 |
| A Yield and Speed Enhancement Scheme under Within-die Variations on 90nm LUT Array | K. Katsuki, M. Kotani, K. Kobayashi, and H. Onodera | Custom Integrated Circuit Conference, pp. 601-604, 2005/09 |
| A Resource-shared VLIW Processor Architecture for Area-efficient On-chip Multiprocessing | K. Kobayashi, M. Aramoto, Y. Yuyama, A. Higuchi, and H. Onodera | Asia and South Pacific Design Automation Conference, pp. 619-622, 2005/01 |
| An Analytical Power Model for Synthesized Register Files Considering address Dependencies | A. Higuchi, K. Kobayashi, and H. Onodera | Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 41-46, 2004/10 |
| Dynamic Voltage and Frequency Scaling Techniques for Heterogeneous Multi-Processor Architecture in Future Nanometer Technologies | Y. Takatsukasa, K. Kobayashi, and H. Onodera | Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 477-482, 2004/10 |
| RTL/ISS Co-Modeling Methodology for Embedded Processor Using SystemC | Y. Yuyama, M. Aramoto, K. Kobayashi, and H. Onodera | International Symposium on Circuits and Systems, vol.V, pp. 305-308, 2004/05 |
| An SoC Architecture and its Design Methodology using Unifunctional Heterogeneous Processor Array | Y. Yuyama, M. Aramoto, K. Kobayashi, and H. Onodera | Asia and South Pacific Design Automation Conference, pp. 737-742, 2004/01 |
| Heterogeneous Processor Architecture and Its Design Methodology to Shorten the Design Period of Embedded SoCs | Y. Yuyama, M. Aramoto, K. Takai, K. Kobayashi, and H. Onodera | Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 351-356, 2003/04 |
| Measurement Results of On-chip IR-drop | K. Kobayashi, J. Yamaguchi, and H. Onodera | Custom Integrated Circuit Conference, pp. 521-524, 2002/05 |
| Hardware and Software Codesign with Using SystemC and Bach | Y. Yuyama, K. Takai, K. Kobayashi, and H. Onodera | DATE Designers' Forum, pp. 30-34, 2002/03 |
| ST: Perl Package for Simulation and Test Environment | K. Kobayashi, and H. Onodera | International Symposium on Circuits and Systems, vol.V, pp. 89-92, 2001/05 |
| A Vector-Pipeline DSP for Low-Rate Videophones | K. Kobayashi, M. Eguchi, T. Iwahashi, T. Shibayama, S. Li, K. Takai, and H. Onodera | Asia and South Pacific Design Automation Conference, pp. 1-2, 2001/01 |
| Vector Quantization Processor for Mobile Video Communication | T. Iwahashi, T. Shibayama, M. Hashimoto, K. Kobayashi, and H. Onodera | SOC/ASIC Conference, pp. 75-79, 2000/09 |
| Physical Insights on Imprint and Application to Functional Memory with Ferroelectric Materials. | Y. Fujii, D. Nagasawa, H. Nozawa, K. Kobayashi, and K. Tamaru | International Symposium on Integrated Ferroelectrics, pp. 274-275, 2000/03 |
| Real Time Low Bit-Rate Video Coding Algorithm Using Multi-Stage Hierarchical Vector Quantization | K. Terada, M. Takeuchi, K. Kobayashi, H. Onodera, and K. Tamaru | International Conference on Acoustics, Speech, and Signal Processing, pp. 2673-2676, 1998/05 |
| A Functional Memory Type Parallel Processor for Vector Quantization | K. Kobayashi, M. Kinoshita, M. Takeuchi, H. Onodera, and K. Tamaru | Asia and South Pacific Design Automation Conference, pp. 665-666, 1997/01 |
| Memory-based Parallel Processor for Vector Quantization | K. Kobayashi, M. Kinoshita, M. Takeuchi, H. Onodera, and K. Tamaru | European Solid-State Circuits Conference, pp. 184-187, 1996/09 |
| A Bit-parallel Block-parallel Functional Memory Type Parallel Processor LSI for Fast Addition and Multiplication | K. Kobayashi, H. Onodera, and K. Tamaru | VLSI Circuit Symposium, pp. 61-62, 1995/06 |
| title | author | taken |
| Ultra-Long-Term Measurement Results of Aging Degradation of Ring Oscillators in a 65 nm FDSOI Process,pdf | T. Kishita, R. Kishida, and K. Kobayashi | Design Automation Symposium, pp. 149-155, 2023/08, Kaga, Ishikawa |
| Measurement Evaluation of Aging Degradation Phenomena Using Stress Separation Starved Oscillators,pdf | R. Toda, R. Kishida, K. Kobayashi, T. Matsuura, R. Miyauchi, and A. Hyogo | Design Automation Symposium, pp. 193-198, 2023/08, Kaga, Ishikawa |
| Measurement Results of Nonvolatile Flip-Flops Using FiCC for IoT Processors with Intermittent Operations ,pdf[URL] | Y. Abe, K. Kobayashi, and O. Hiroyuki | IEICE Technical Report (VLD), VLD2021-85, pp. 45-50, 2022/03 |
| [Panel Discussion] The Role of System and Signal Processing Subsociety -Challenging the loT (Internet of Things) Problem-,pdf[URL] | H. Okazaki, H. Sato, K. Kobayashi, A. Ozaki, K. Hayashi, and T. Tanaka | IEICE Technical Report (VLD), VLD2021-04, pp. 16-18, 2021/07 |
| Evaluation of Dynamic Characteristics of SiC MOSFET and JFET for Swiching at 13.56MHz,pdf | S. Inamori, J. Furuta, and K. Kobayashi | , 4-011, pp. 11, 2016/03 |
| Methodology for Reduction of Timing Margin by Considering Correlation between Process Variation and BTI[URL] | M. Yabuuchi, and K. Kobayashi | IEICE Technical Report (VLD), VLD2014-163, pp. 61-66, 2015/03, Naha, Japan |
| Initial Frequency Degradation on Ring Oscillators in 65-nm SOTB Process Caused by Plasma-Induced Damage,pdf[URL] | A. Oshima, R. Kishida, M. Yabuuchi, and K. Kobayashi | IEICE Technical Report (ICD), ICD2014-48, pp. 93-98, 2014/08, Sapporo, Japan |
| A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14μA Sleep Current using Reverse-Body-Bias Assisted 65nm SOTB CMOS Technology[URL] | K. Ishibashi, N. Sugii, K. Usami, A. Hideharu, K. Kobayashi, P. Cong-Kha, H. Makiyama, Y. Yoshiki , H. Shinohara, T. Iwamatsu, Y. Yamaguchi, H. Oda, T. Hasegawa, S. Okanishi, H. Yanagita, S. Kamohara, M. Kadoshima, K. Maekawa, T. Yamashita, D. Le, T. Yomogita, M. Kudo, K. Kitamori, S. Kondo, and Y. Manzawa | IEICE Technical Report (ICD), ICD2014-31, pp. 1-4, 2014/08, Sapporo, Japan |
| Reliability on Integrated Circuits -Details of Soft Errors -,pdf[URL] | K. Kobayashi | IEICE Technical Report (ICD), ICD2013-134, pp. 81, 2014/01, Kyoto, Japan |
| Evaluation of Soft-error Tolenrance of Fully-Depleted Silicon on Insulators(FDSOI) by Circuit Simulations,pdf | S. Kanda, and K. Kobayashi | Electronics Society Conference of IEICE, C-12-38, pp. 98, 2013/09, Fukuoka, Japan |
| Analysis of Radiation-hard Standard Layout Structure,pdf | K. Zhang, and K. Kobayashi | Design Automation Symposium, pp. 115-120, 2013/08, Gihu, Japan |
| A Transistor Model for Transient Simulation of Aging Degradation with Verilog-A,pdf | R. Kishida, and K. Kobayashi | Design Automation Symposium, pp. 67-72, 2013/08, Gihu, Japan |
| Impact of Random Telegraph Noise on CMOS Logic Delay Uncertainty,pdf[URL] | T. Matsumoto, K. Kobayashi, and H. Onodera | General Conference of IEICE, C-12-54, pp. 125, 2013/03 |
| Robust Redundant Circuit for Circuit Time-Dependent Deterioration by Reversing Resister Values,pdf[URL] | S. Okada, J. Yao, H. Shimada, and K. Kobayashi | IEICE Technical Report (VLD), VLD2012-162, pp. 147-152, 2013/03, Naha, Japan |
| Measurement of Multiple Cell Upset according to the Distances between Latches on Flip-Flops,pdf | J. Furuta, K. Kobayashi, and H. Onodera | Engineering Sciences Society Conference of IEICE, A-3-7, pp. 54, 2012/09, Toyama, Japan |
| Characteristics of An NBTI Measurement Circuit to Reduce Switching Time between Degradation Mode and Recovery Mode,pdf | A. Miki, T. Matsumoto, K. Kobayashi, and H. Onodera | Electronics Society Conference of IEICE, C-12-44, pp. 117, 2012/09, Toyama, Japan |
| Soft-error Tolenrance of SOI Transisitors according to the Thickness of the BOX Layer,pdf | K. Zhang, and K. Kobayashi | Engineering Sciences Society Conference of IEICE, A-3-8, pp. 55, 2012/09, Toyama, Japan |
| Impact of NBTI and RTN on CMOS Digital Circuit and SRAM,pdf | T. Matsumoto, K. Kobayashi, and H. Onodera | Design Automation Symposium, pp. 151-156, 2012/08, Gero, Japan |
| An NBTI Measurement Circuit for Reduction of Switching Time between Degradation and Recovery Mode,pdf | A. Miki, T. Matsumoto, K. Kobayashi, and H. Onodera | General Conference of IEICE, C-12-24, 2012/03, Okayama, Japan |
| Soft Error Immunity on Redundant Flip-Flops with Heavy Ion Beams,pdf | K. Murakami, R. Yamamoto, and K. Kobayashi | General Conference of IEICE, C-12-14, 2012/03, Okayama, Japan |
| A 65-nm Radiation-Hard Flip-Flop Tolerant to Multiple Cell Upsets,pdf[URL] | R. Yamamoto, C. Hamanaka, J. Furuta, K. Kobayashi, and H. Onodera | IEICE Technical Report (ICD), ICD2011-129, pp. 131-136, 2011/12, Osaka, Japan |
| Multi-core LSI Lifetime Extension by NBTI-Recovery-based Self-healing,pdf | T. Matsumoto, H. Makino, K. Kobayashi, and H. Onodera | IEICE Technical Report (ICD), ICD2011-92, pp. 59-63, 2011/11, Miyazaki, Japan |
| Performance Evaluation of Soft-Error Tolerant Multiple Modular Processors Implemented with Redundant and Non-Redundant Flip-Flops ,pdf | S. Okada, M. Masuda, J. Yao, H. Shimada, and K. Kobayashi | IEICE Technical Report (VLD), VLD2011-59, pp. 43-48, 2011/11, Miyazaki, Japan |
| Degradation of Oscillation Frequency of Ring Oscillators Placed on a 90 nm FPGA,pdf | S. Ishii, and K. Kobayashi | IEICE Technical Report (VLD), VLD2011-55, pp. 19-24, 2011/11, Miyazaki, Japan |
| Soft Error Immunity on Multiple Modular Processors with Redundant or Non-Redundant Flip Flops,pdf | S. Okada, M. Masuda, J. Yao, H. Shimada, and K. Kobayashi | Engineering Sciences Society Conference of IEICE, A-3-12, 2011/09, Sapporo, Japan |
| Analytical Approach for NBTI-Induced Degradation with RTN Model,pdf | M. Yabuuchi, and K. Kobayashi | Engineering Sciences Society Conference of IEICE, A-3-9, 2011/09, Sapporo, Japan |
| Comparative specification with error resistance between DFF and Dual Modular Redundancy FFs,pdf | K. Kubota, and K. Kobayashi | Electronics Society Conference of IEICE, C-12-22, 2011/09, Sapporo, Japan |
| Measurement and Its Modeling of Digital Circuit Delay Degradation,pdf | T. Matsumoto, K. Kobayashi, and H. Onodera | Electronics Society Conference of IEICE, C-12-20, 2011/09, Sapporo, Japan |
| Measurement Circuit for SET pulse width using Propagation-Induced Pulse Shrinking,pdf | J. Furuta, K. Kobayashi, and H. Onodera | Electronics Society Conference of IEICE, C-12-21, 2011/09 |
| Analytical Approach for NBTI-Induced Delay with RTN Model on FPGA Routing Architecture,pdf | M. Yabuuchi, and K. Kobayashi | Design Automation Symposium, pp. 189-194, 2011/09, Gero, Gifu, Japan |
| RTN-Induced Propagation Delay Fluctuation of Digital Circuits,pdf | T. Matsumoto, K. Ito, K. Kobayashi, and H. Onodera | Design Automation Symposium, pp. 87-92, 2011/08, Gero, Gifu, Japan |
| Evaluation of soft Error Rates based on the Parasitic Bipolar Effects from Circuit-Level Simulation,pdf | J. Furuta, C. Hamanaka, K. Kobayashi, and H. Onodera | Design Automation Symposium, pp. 81-86, 2011/08, Gero, Gifu, Japan |
| Design Methodology of On-Chip Power Distribution Network Considering Package Parasitic Resistance,pdf | S. Nishizawa, K. Kobayashi, and H. Onodera | Design Automation Symposium, pp. 45-50, 2011/08, Gero, Gifu, Japan |
| Measurement Results of Variation of Dual Modular Redundancy Flip-Flop to Protect Soft Errors,pdf | C. Hamanaka, R. Yamamoto, and K. Kobayashi | General Conference of IEICE, A-3-4, 2011/03, Tokyo, Japan |
| A 65nm CMOS High-Speed and High-Fidelity NBTI Recovery Sensor,pdf[URL] | T. Matsumoto, H. Makino, K. Kobayashi, and H. Onodera | IEICE Technical Report (ICD), ICD2010-104, pp. 55-58, 2010/12, Tokyo, Japan |
| A Dual-Modular Redundancy Flip-Flop Toralent to Soft Errors,pdf | K. Kobayashi | Engineering Sciences Society Conference of IEICE, AT-1-4, 2010/09, Sakai, Japan |
| The Simple Layout TEG for Measuring Variation,pdf | C. Hamanaka, and K. Kobayashi | Engineering Sciences Society Conference of IEICE, A-3-5, 2010/09, Sakai, Japan |
| Evaluation of the impact of a Random Telegraph Noise on Combinational Circuits,pdf | K. Ito, T. Matsumoto, K. Kobayashi, and H. Onodera | Design Automation Symposium, pp. 99-104, 2010/09, Toyohashi, Japan |
| Measurement Results of Neutron-Induced SET Pulse Width Using Propagation-Induced Pulse Narrowing in 65nm Process,pdf | J. Furuta, K. Kobayashi, and H. Onodera | Design Automation Symposium, pp. 233-238, 2010/09, Toyohashi, Japan |
| Circuit Performance Degradation on FPGAs Considering NBTI and Process Variations,pdf | M. Yabuuchi, and K. Kobayashi | Design Automation Symposium, pp. 135-140, 2010/09, Toyohashi, Japan |
| A 65nm Bistable Cross-coupled Dual Modular Redundancy Flip-Flop Capable of Protecting Soft Errors on the C-element,pdf | J. Furuta, C. Hamanaka, K. Kobayashi, and H. Onodera | IEICE Technical Report (ICD), ICD2010-61, pp. 121-124, 2010/08, Sapporo, Japan |
| An Instruction Decomposition Scheme to Aid Fine-Grained Online Recovery in Pipeline Processors | H. Shimada, J. Yao, and K. Kobayashi | General Conference of IEICE, D-10-6, 2010/03, Sendai, Japan |
| NBTI Degradation and Recovery Measurement by Subthreshold Leakage Current,pdf | H. Makino, T. Matsumoto, K. Kobayashi, and H. Onodera | General Conference of IEICE, C-12-68, 2010/03, Sendai, Japan |
| Generation Mechanism of SEU and MCU Caused by Parasitic Lateral Bipolar Transistors,pdf | C. Hamanaka, J. Furuta, H. Makino, K. Kobayashi, and H. Onodera | IEICE Technical Report (VLD), VLD2009-103, pp. 25-30, 2010/03, Naha, Japan |
| A Circuit to Measure the Frequency Dependance of NBTI,pdf | H. Makino, K. Kobayashi, and H. Onodera | Electronics Society Conference of IEICE, C-12-30, pp. 94, 2009/09, Niigata, Japan |
| Estimation of Process Parameter Variation using Delay Monitor Circuits,pdf | I. A.K.M Mahfuzul, A. Tsuchiya, K. Kobayashi, and H. Onodera | Design Automation Symposium, pp. 127-132, 2009/08, Kaga, Japan |
| Effect of Within-Die Variation on Sequencial Circuits Characteristics,pdf | H. Sunagawa, A. Tsuchiya, K. Kobayashi, and H. Onodera | Design Automation Symposium, pp. 85-90, 2009/08, Kaga, Japan |