List of Publications

Journal Papers

titleauthortaken
A Radiation-Hardened Non-Redundant Flip-Flop, Stacked Leveling Critical Charge Flip-Flop in a 65 nm Thin BOX FD-SOI Process,pdf[URL]J. Furuta, J. Yamaguchi, and K. KobayashiIEEE Trans. on Nuclear Science, vol.63, no. 4, pp. 2080-2086, 2016/08
Analysis of Soft Error Rates in 65- and 28-nm FD-SOI Processes Depending on BOX Region Thickness and Body Bias by Monte-Carlo Based Simulations,pdf[URL]K. Zhang, S. Umehara, J. Yamaguchi, J. Furuta, and K. KobayashiIEEE Trans. on Nuclear Science, vol.63, no. 4, pp. 2002-2009, 2016/08
Size Optimization Technique for Logic Circuits that Considers BTI and Process Variations,pdf[URL]M. Yabuuchi, and K. KobayashiIPSJ Transactions on System LSI Design Methodology, vol.9, pp. 72-78, 2016/08
A Perpetuum Mobile 32bit CPU on 65nm SOTB CMOS Technology with Reverse-Body-Bias Assisted Sleep Mode,pdf[URL]K. Ishibashi, N. Sugii, S. Kamohara, K. Usami, A. Hideharu, K. Kobayashi, and P. Cong-KhaIEICE Trans. on Electronics, vol.E98-C, no. 7, pp. 536-543, 2015/07
Impact of Cell Distance and Well-contact Density on Neutron-induced Multiple Cell Upsets,pdf[URL]J. Furuta, K. Kobayashi, and H. OnoderaIEICE Trans. on Electronics, vol.E98-C, no. 4, pp. 1745-1353, 2015/04
Initial and long-term frequency degradation of ring oscillators caused by plasma-induced damage in 65 nm bulk and fully depleted silicon-on-insulator processes ,pdf[URL]R. Kishida, A. Oshima, M. Yabuuchi, and K. KobayashiJapanese Journal of Applied Physics, vol.54, no. 4S, pp. 04DC19-1-5, 2015/03
Radiation hardness evaluations of 65nm fully depleted silicon on insulator and bulk processes by measuring single event transient pulse widths and single event upset rates,pdf[URL]J. Furuta, E. Sonezaki, and K. KobayashiJapanese Journal of Applied Physics, vol.54, no. 4S, pp. 04DC15-1-6, 2015/03
Correlations between BTI-Induced Degradations and Process Variations on ASICs and FPGAs,pdf[URL]M. Yabuuchi, R. Kishida, and K. KobayashiIEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol.E97-A, no. 12, pp. 2367-2372, 2014/12
Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing,pdf[URL]H. Kounoura, D. Dawood, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, O. Hiroyuki, T. Imagawa, K. Wakabayashi, M. Hashimoto, T. Onoye, and H. OnoderaIEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol.E97-A, no. 12, pp. 2518-2529, 2014/12
EReLA: A Low-Power Reliable Coarse-Grained Reconfigurable Architecture Processor and Its Irradiation Tests ,pdf[URL]J. Yao, M. Saito, S. Okada, K. Kobayashi, and Y. NakashimaIEEE Trans. on Nuclear Science, vol.61, no. 6, pp. 3250-3257, 2014/12
A Low-Power and Area-Efficient Radiation-Hard Redundant Flip-Flop, DICE ACFF, in a 65 nm Thin-BOX FD-SOI ,pdfK. Kobayashi, K. Kubota, M. Masuda, Y. Manzawa, J. Furuta, S. Kanda, and H. OnoderaIEEE Trans. on Nuclear Science, vol.61, no. 4, pp. 1881-1888, 2014/08
Dependence of Cell Distance and Well-Contact Density on MCU Rates by Device Simulations and Neutron Experiments in a 65-nm Bulk Process ,pdfK. Zhang, J. Furuta, K. Kobayashi, and H. OnoderaIEEE Trans. on Nuclear Science, vol.61, no. 4, pp. 1583-1589, 2014/08
A 65 nm Low-Power Adaptive-Coupling Redundant Flip-Flop,pdf[URL]M. Masuda, K. Kubota, R. Yamamoto, J. Furuta, K. Kobayashi, and H. OnoderaIEEE Trans. on Nuclear Science, vol.60, no. 4, pp. 2750 - 2755 , 2013/08
A Radiation-Hard Redundant Flip-Flop to Suppress Multiple Cell Upset by Utilizing the Parasitic Bipolar Effect,pdf[URL]K. Zhang, J. Furuta, R. Yamamoto, K. Kobayashi, and H. OnoderaIEICE Trans. on Electronics, vol.E96-C, no. 2, pp. 511-517, 2013/04
Impact of Body-Biasing Technique on Random Telegraph Noise Induced Delay Fluctuation,pdf[URL]T. Matsumoto, K. Kobayashi, and H. OnoderaJapanese Journal of Applied Physics, vol.52, pp. 04CE05, 2013/03
Effects of Neutron-Induced Well Potential Perturbation for Multiple Cell Upset of Flip-Flops in 65 nm,pdf[URL]J. Furuta, R. Yamamoto, K. Kobayashi, and H. OnoderaIEEE Trans. on Nuclear Science, vol.60, no. 1, pp. 213-218, 2013/01
Higher-Order Effect of Source-Drain Series Resistance on Saturation Drain Current in Sub-20nm Metal-Oxide-Semiconductor Field-Effect Transistors,pdf[URL]J. Yoon, A. Hiroki, and K. KobayashiJapanese Journal of Applied Physics, vol.51, pp. 111101-1-111101-5, 2012/12
DARA: A Low-Cost Reliable Architecture Based on Unhardened Devices and Its Case Study of Radiation Stress Test ,pdf[URL]J. Yao, S. Okada, M. Masuda, K. Kobayashi, and Y. NakashimaIEEE Trans. on Nuclear Science, vol.59, no. 6, pp. 2852 - 2858 , 2012/12
NBTI-Induced Delay Degradation Analysis of FPGA Routing Structures ,pdf[URL]M. Yabuuchi, and K. KobayashiIPSJ Transactions on System LSI Design Methodology, vol.5, pp. 143-149, 2012/08
Variation-Sensitive Monitor Circuits for Estimation of Global Process Parameter Variation,pdf[URL]I. A.K.M Mahfuzul, A. Tsuchiya, K. Kobayashi, and H. OnoderaIEEE Transacition on Semiconductor Manufacturing, vol.25, no. 4, pp. 571-580, 2012/05
Multicore Large-Scale Integration Lifetime Extension by Negative Bias Temperature Instability Recovery-Based Self-Healing,pdf[URL]T. Matsumoto, H. Makino, K. Kobayashi, and H. OnoderaJapanese Journal of Applied Physics, vol.51, no. 4, 2012/04
An Area-efficient 65 nm Radiation-Hard Dual-Modular Flip-Flop to Avoid Multiple Cell Upsets,pdf[URL]R. Yamamoto, C. Hamanaka, J. Furuta, K. Kobayashi, and H. OnoderaIEEE Trans. on Nuclear Science, vol.58, no. 6, pp. 3053 - 3059, 2011/12
Variation-Tolerance of a 65-nm Error-Hardened Dual-Modular-Redundancy Flip-Flop Measured by Shift-Register-Based Monitor Structures,pdf[URL]C. Hamanaka, R. Yamamoto, J. Furuta, K. Kubota, K. Kobayashi, and H. OnoderaIEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol.E94-A, no. 12, pp. 2669-2675, 2011/12
A 65 nm Complementary Metal-Oxide-Semiconductor 400 ns Measurement Delay Negative-Bias-Temperature-Instability Recovery Sensor with Minimum Assist Circuit,pdf[URL]T. Matsumoto, H. Makino, K. Kobayashi, and H. OnoderaJapanese Journal of Applied Physics, vol.50, no. 4, pp. 04DE06, 2011/04
An Area/Delay Efficient Dual-Modular Flip-Flop with Higher SEU/SET Immunity,pdf[URL]J. Furuta, K. Kobayashi, and H. OnoderaIEICE Trans. on Electronics, vol.E93-C, no. 2, pp. 340-346, 2010/03
Effect of Regularity-Enhanced Layout on Variability and Circuit Performance of Standard Cells,pdf[URL]H. Sunagawa, H. Terada, A. Tsuchiya, K. Kobayashi, and H. OnoderaIPSJ Transactions on System LSI Design Methodology, vol.3, pp. 130-139, 2010/02
Micro/nanoimprinting of Glass under High Temperature Using a CVD Diamond MoldM. Komori, H. Uchiyama, H. Takebe, T. Kusuura, K. Kobayashi, K. Kuwahara, and T. TsuchiyaJournal of Micromechanics and Microengineering, 065013, 2008/05
A 90nm 48x48 LUT-Based FPGA Enhancing Speed and Yield Utilizing Within-Die Delay VariationsK. Kobayashi, K. Katsuki, M. Kotani, Y. Sugihara, Y. Kume, and H. OnoderaIEICE Trans. on Electronics, vol.E90-C, no. 10, pp. 1919-1926, 2007/10
A 90 nm LUT Array for Speed and Yield Enhancement by Utilizing Within-Die Delay VariationsK. Katsuki, M. Kotani, K. Kobayashi, and H. OnoderaIEICE Trans. on Electronics, vol.E90-C, no. 4, pp. 699-707, 2007/04
A Leakage Reduction Scheme for Sleep Transistors with Decoupling Capacitors in the Deep Submicron EraK. Kobayashi, A. Higuchi, and H. OnoderaIEICE Trans. on Electronics, vol.E89-C, no. 6, pp. 838-843, 2006/06
Alternative Self-Shielding for High-Speed and Reliable On-Chip Global InterconnectY. Yuyama, A. Tsuchiya, K. Kobayashi, and H. OnoderaIEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol.E89-C, no. 3, pp. 327-333, 2006/03
A resource-Shared VLIW Processor for Low-power On-Chip Multiprocessing in the Nanometer Era,pdfK. Kobayashi, M. Aramoto, and H. OnoderaIEICE Trans. on Electronics, vol.E88-C, no. 4, pp. 552-558, 2005/04
Instruction-Level Power Estimation Method by Considering Hamming Distance of RegistersA. Higuchi, K. Kobayashi, and H. OnoderaIEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol.E87-A, no. 4, pp. 823-829, 2004/04
An Efficient Motion Estimation Algorithm Using a Gyro SensorK. Kobayashi, R. Nakanishi, and H. OnoderaIEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol.E87-A, no. 3, pp. 530-538, 2004/03
A Comprehensive Simulation and Test Environment for Prototype VLSI VerificationK. Kobayashi, and H. OnoderaIEICE Trans. on Inf. & Syst., vol.E87-D, no. 3, pp. 630-636, 2004/03
A Low-Power High-Performance Vector-Pipeline DSP for Low-Rate VideophonesK. Kobayashi, M. Eguchi, T. Iwahashi, T. Shibayama, S. Li, K. Takai, and H. OnoderaIEICE Trans. on Electronics, vol.E84-C, no. 2, pp. 193-201, 2001/02
Physical Insights on Imprint and Application to Functional Memory with Ferroelectric MaterialsY. Fujii, D. Nagasawa, H. Nozawa, K. Kobayashi, and K. TamaruInternational Journal on Integrated Ferroelectrics, vol.33, no. 1-4, pp. 261-270, 2001/01
Architecture and Performance Evaluation of a New Functional Memory: Functioal Memory for AdditionK. Kobayashi, M. Yamaoka, Y. Kobayashi, H. Onodera, and K. TamaruIEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol.E83-A, no. 12, pp. 2400-2408, 2000/12
A Real-Time Low-Rate Video Compression Algorithm Using Multi-Stage Hierarchical Vector QuantizationK. Kobayashi, K. Terada, H. Onodera, and K. TamaruIEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol.E82-A, no. 2, pp. 215-222, 1999/02
Memory Based Architecture and its Implementation Scheme Named Bit-Parallel Block-Parallel Functional Memory Type Parallel Processor BPBP FMPPK. Tamaru, K. Kobayashi, and H. OnoderaComputers and Electrical Engineering, vol.24, pp. 17-31, 1998/06
An LSI for Low Bit-Rate Image Compression Using Vector QuantizationK. Kobayashi, N. Nakamura, K. Terada, H. Onodera, and K. TamaruIEICE Trans. on Electronics, vol.Vol.E81-C, no. No.5, pp. 718-724, 1998/05
A memory-based parallel processor for vector quantization: FMPP-VQ.K. Kobayashi, M. Kinoshita, M. Takeuchi, H. Onodera, and K. TamaruIEICE Trans. on Electronics, vol.E80-C, no. 7, pp. 970--975, 1997/07
A bit-parallel block-parallel functional memory type parallel processor architectureK. Kobayashi, K. Tamaru, H. Yasuura, and H. OnoderaIEICE Trans. on Electronics, vol.E76-C, no. 7, pp. 1151-1158, 1993/07

International Confenrence (w/ Review)

titleauthortaken
Plasma Induced Damage Depending on Antenna Layers in Ring Oscillators,pdfR. Kishida, J. Furuta, and K. KobayashiInternational Conference on Solid State Devices and Materials, pp. 209-210, 2017/09, Sendai, Japan
MHz-Switching-Speed Current-Source Gate Driver for SiC Power MOSFETs,pdf[URL]S. Inamori, J. Furuta, and K. KobayashiEuropean Conference on Power Electronics and Applications, pp. DS1a.2.1-2.7, 2017/09, Warsaw, Poland
Analysis of Neutron-induced Soft Error Rates on 28nm FD-SOI and 22nm FinFET Latches by the PHITS-TCAD Simulation System,pdfJ. Furuta, S. Umehara, and K. Kobayashi International Conference on Simulation of Semiconductor Processes and Devices , pp. 185-188, 2017/09, Kamakura, Japan
An Accurate Metric to Control Time Step of Transient Device Simulation by Matrix Exponential Method,pdfS. Kumashiro, T. Kamei, A. Hiroki, and K. Kobayashi International Conference on Simulation of Semiconductor Processes and Devices , pp. 37-40, 2017/09, Kamakura, Japan
Design of RCD Snubber Considering Wiring Inductance for MHz-Switching of SiC-MOSFET,pdf[URL]Y. Yamashita, J. Furuta, S. Inamori, and K. KobayashiIEEE Workshop on Control and Modeling for Power Electronics, O10-2, 2017/07, Stanford, CA, USA
Circuit-level Simulation Methodology for Random Telegraph Noise by Using Verilog-AMS,pdfT. Komawaki, M. Yabuuchi, R. Kishida, J. Furuta, T. Matsumoto, and K. KobayashiInternational Conference on IC Design and Technology, I2, pp. I2.01-04, 2017/05, Austin, TX, USA
A Flip-Flop with High Soft-error Tolerance and Small Power and Delay Overheads,pdfK. Yamada, H. Maruoka, J. Furuta, and K. KobayashiSymposium on Low-Power and High-Speed Chips (COOL Chips), poster-1, 2017/04, Yokohama, Japan
A 16 nm FinFET Radiation-hardened Flip-Flop, Bistable Cross-coupled Dual-Modular-Redundancy FF for Terrestrial and Outer-Space Highly-reliable Systems,pdf[URL]K. Kobayashi, J. Furuta, H. Maruoka, M. Hifumi, S. Kumashiro, T. Kato, and S. KohriIEEE International Reliability Physics Symposium, pp. SE2.1-SE2.3, 2017/04, Monterey, CA, USA
Influence of Layout Structures to Soft Errors Caused by Higher-energy Particles on 28/65 nm FDSOI Flip-Flops,pdf[URL]M. Hifumi, H. Maruoka, S. Umehara, K. Yamada, J. Furuta, and K. KobayashiIEEE International Reliability Physics Symposium, pp. SE5.1-SE5.4, 2017/04, Monterey, CA, USA
Circuit Analysis and Defect Characteristics Estimation Methods Using Bimodal Defect-Centric Random Telegraph Noise Model,pdf[URL]M. Yabuuchi, A. Oshima, T. Komawaki, R. Kishida, J. Furuta, K. Kobayashi, P. Weckx, B. Kaczer, T. Matsumoto, and H. OnoderaInternational Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, pp. 47-52, 2017/03, Monterey, CA
Degradation Caused by Negative Bias Temperature Instability Depending on Body Bias on NMOS or PMOS in 65 nm Bulk and Thin-BOX FDSOI Processes,pdfR. Kishida, and K. KobayashiElectron Devices Technology and Manufacturing, pp. 122-123, 2017/03, Toyama, Japan
The Impact of RTN-Induced Temporal Performance Fluctuation Against Static Performance Variation,pdfT. Matsumoto, K. Kobayashi, and H. OnoderaElectron Devices Technology and Manufacturing, pp. 31-32, 2017/03
A Low Surge Voltage and Fast Speed Gate Driver for SiC MOSFET with Switched Capacitor Circuit,pdf[URL]M. Fei, J. Furuta, and K. Kobayashi Workshop on Wide Bandgap Power Devices and Applications, pp. 282-285, 2016/11, Arkansas, USA
A Radiation-hard Layout Structure to Control Back-Gate Biases in a 65 nm Thin-BOX FDSOI Process,pdfJ. Yamaguchi, J. Furuta, and K. KobayashiSOI-3D-Subthreshold Microelectronics Technology Unified Conference, pp. 28-30, 2016/10, Burlingame, CA, USA
Correlations between Plasma Induced Damage and Negative Bias Temperature Instability in 65 nm Bulk and Thin-BOX FDSOI Processes,pdfR. Kishida, and K. KobayashiSOI-3D-Subthreshold Microelectronics Technology Unified Conference, pp. 25-27, 2016/10, Burlingame, CA, USA
Negative Bias Temperature Instability by Body Bias on Ring Oscillators in Thin BOX Fully-Depleted Silicon on Insulator Process,pdfR. Kishida, and K. KobayashiInternational Conference on Solid State Devices and Materials, pp. 711-712, 2016/09, Tsukuba, Japan
A Non-Redundant Low-Power Flip Flop with Stacked Transistors in a 65 nm Thin BOX FDSOI Process,pdfH. Maruoka, M. Hifumi, J. Furuta, and K. KobayashiThe conference on Radiation and its Effects on Components and Systems, 2016/09, Bremen, Germany
Physical-Based RTN Modeling of Ring Oscillators in 40-nm SiON and 28-nm HKMG by Bimodal Defect-Centric Behaviors,pdfA. Oshima, T. Komawaki, K. Kobayashi, R. Kishida, P. Weckx, B. Kaczer, T. Matsumoto, and H. Onodera International Conference on Simulation of Semiconductor Processes and Devices , pp. 327-330, 2016/09, Nurnberg, Germany
Soft Error Tolerance of Redundant Flip-Flops by Heavy-Ion Beam Tests in 65 nm bulk and FDSOI ProcessesE. Sonezaki, M. Hifumi, J. Furuta, and K. KobayashiIEEE Nuclear and Space Radiation Effects Conference, 2016/07, Portland, USA
Correlations between Radiation Hardness and Variation of FFs Depending on Layout Structures in a 28 nm Thin BOX FD-SOI Process by Alpha Particle Irradiation,pdfH. Maruoka, M. Hifumi, S. Kanda, J. Furuta, and K. KobayashiSilicon Errors in Logic - System Effects, 2016/03, Austion, TX
Analysis of Terrestrial Single Event Upsets by Body Biases in a 28 nm UTBB Process by a PHITS-TCAD Simulation System,pdfS. Umehara, K. Zhang, S. Kanda, M. Hifumi, J. Furuta, and K. KobayashiInternational Workshop on Radiation Effects on Semiconductor Devices for Space Applications, pp. 53-56, 2015/11, Kiryu, Gunma, Japan
Radiation Hardness Evaluations of FFs on 28nm and 65nm Thin BOX FD-SOI Processes by Heavy-Ion Irradiation,pdfM. Hifumi, E. Sonezaki, J. Furuta, and K. KobayashiInternational Workshop on Radiation Effects on Semiconductor Devices for Space Applications, pp. 93-96, 2015/11, Kiryu, Gunma, Japan
Estimation of Soft Error Tolerance according to the Thickness of Buried Oxide and Body Bias 28-nm and 65-nm in FD-SOI Processes by a Monte-Carlo Simulation,pdfK. Zhang, J. Yamaguchi, S. Kanda, J. Furuta, and K. KobayashiInternational Conference on Solid State Devices and Materials, pp. 1026-1027, 2015/09, Sapporo, Japan
A Radiation-Hardened Non-redundant Flip-Flop, Stacked Leveling Critical Charge Flip-Flop in a 65 nm Thin BOX FD-SOI Process,pdf[URL]J. Yamaguchi, J. Furuta, and K. KobayashiThe conference on Radiation and its Effects on Components and Systems, 2015/09, Moscow, Russia
Analysis of BOX Layer Thickness on SERs of 65 and 28nm FD-SOI Processes by a Monte-Carlo Based Simulation Tool,pdf[URL]K. Zhang, S. Kanda, J. Yamaguchi, J. Furuta, and K. KobayashiThe conference on Radiation and its Effects on Components and Systems, 2015/09, Moscow, Russia
Analysis of the Soft Error Rates on 65-nm SOTB and 28-nm UTBB FD-SOI Structures by a PHITS- TCAD Based Simulation Tool,pdfK. Zhang, S. Kanda, J. Yamaguchi, J. Furuta, and K. Kobayashi International Conference on Simulation of Semiconductor Processes and Devices , 2015/09, Washington DC, USA
Impact of Random Telegraph Noise on Ring Oscillators Evaluated by Circuit-level Simulations,pdfA. Oshima, P. Weckx, B. Kaczer, K. Kobayashi, and T. MatsumotoInternational Conference on IC Design and Technology, 2015/06, Leuven, Bergium
Negative Bias Temperature Instability Caused by Plasma Induced Damage in 65 nm Bulk and Silicon On Thin BOX (SOTB) Processes,pdf[URL]R. Kishida, A. Oshima, and K. KobayashiIEEE International Reliability Physics Symposium, pp. CA.2.1-CA.2.5, 2015/04, Monterey, CA, USA
Analysis of Soft Error Rates by Supply Voltage in 65-nm SOTB and 28-nm UTBB Structures by a PHITS-TCAD Simulation System,,pdf[URL]K. Zhang, S. Kanda, J. Yamaguchi, J. Furuta, and K. KobayashiSilicon Errors in Logic - System Effects, 2015/03, Austin, TX, USA
Analysis of the Distance Dependent Multiple Cell Upset Rates on 65-nm Redundant Latches by a PHITS-TCAD Simulation System,pdfK. Zhang, J. Furuta, and K. KobayashiWorkshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 89-93, 2015/03, Jiaosi, Yilan, Taiwan
Reliability-Configurable Mixed-Grained Reconfigurable Array Compatible with High-Level Synthesis,pdf[URL]M. Hashimoto, D. Dawood, H. Kounoura, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, O. Hiroyuki, T. Imagawa, K. Wakabayashi, T. Onoye, and H. OnoderaAsia and South Pacific Design Automation Conference, pp. 14 - 15, 2015/01, Chiba, Japan
Initial Frequency Degradation and Variation on Ring Oscillators from Plasma Induced Damage in Fully-Depleted Silicon on Insulator Process,pdf[URL]R. Kishida, A. Oshima, M. Yabuuchi, and K. KobayashiIEEE/ACM Workshop on Variability Modeling and Characterization, 2014/11, San Jose, CA, USA
Initial and Long-Term Frequency Degradation on Ring Oscillators from Plasma Induced Damage in 65 nm Bulk and Silicon On Thin BOX processes,pdfR. Kishida, A. Oshima, M. Yabuuchi, and K. KobayashiInternational Conference on Solid State Devices and Materials, pp. 52-53, 2014/09, Tsukuba, Japan
Radiation Hardness Evaluations of 65 nm FD-SOI and Bulk processes by Measuring SET Pulse Widths and SEU Rates,pdfE. Sonezaki, J. Furuta, and K. KobayashiInternational Conference on Solid State Devices and Materials, pp. 840-841, 2014/09, Tsukuba, Japan
Correlation between BTI-Induced Degradations and Process Variations by Measuring Frequency of ROs ,pdfM. Yabuuchi, R. Kishida, and K. KobayashiInternational Meeting for Future of Electron Devices, Kansai, pp. 128-131, 2014/06, Kyoto, Japan
Impact of Body Bias on Soft Error Tolerance of Bulk and Silicon on Thin BOX Structure in 65-nm Process,pdfK. Zhang, Y. Manzawa, and K. KobayashiIEEE International Reliability Physics Symposium, pp. SE2.1-SE2.4, 2014/06, Waicoloa, Hawaii
A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14A Sleep Current using Reverse Body Bias Assisted 65nm SOTB CMOS Technology,pdfK. Ishibashi, N. Sugii, K. Usami, A. Hideharu, K. Kobayashi, P. Cong-Kha, H. Makiyama, Y. Yoshiki , H. Shinohara, T. Iwamatsu, Y. Yamaguchi, H. Oda, T. Hasegawa, S. Okanishi, H. Yanagita, S. Kamohara, M. Kadoshima, K. Maekawa, T. Yamashita, D. Le, T. Yomogita, M. Kudo, K. Kitamori, S. Kondo, and Y. ManzawaSymposium on Low-Power and High-Speed Chips (COOL Chips), 2014/04, Yokohama, Japan
Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing,pdfD. Dawood, H. Kounoura, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, Y. Mitsuyama, T. Imagawa, S. Noda, K. Wakabayashi, M. Hashimoto, T. Onoye, and H. OnoderaIEEE Asian Solid-State Circuits Conference, pp. 313-316, 2013/11, Singapore
Radiation-Hard Layout Structures on Bulk and SOI Process by Device-Level Simulations,pdfK. Zhang, and K. KobayashiWorkshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 275-279, 2013/10, Sapporo, Japan
Impact of Drive Strength and Well-Contact Density on Heavy-Ion-Induced Single Event Transient,pdfJ. Furuta, M. Masuda, K. Takeuchi, K. Kobayashi, and H. OnoderaWorkshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 165-169, 2013/10, Sapporo, Japan
Dependence of Cell Distance and Well-contact Density of MCU Rates by Device Simulations and Neutron Experiments in a 65-nm Bulk Process,pdfK. Zhang, J. Furuta, K. Kobayashi, and H. OnoderaThe conference on Radiation and its Effects on Components and Systems, 2013/09, Oxford, UK
A Low-Power and Area-Efficient Radiation-Hard Redundant Flip-Flop, DICE ACFF, in a 65 nm Thin-BOX FD-SOI,pdf[URL]K. Kubota, M. Masuda, J. Furuta, Y. Manzawa, S. Kanda, K. Kobayashi, and H. OnoderaThe conference on Radiation and its Effects on Components and Systems, PC-2, 2013/09, Oxford, UK
Impact of Cell Distance and Well-contact Density on Neutron-induced Multiple Cell Upsets,pdfJ. Furuta, K. Kobayashi, and H. OnoderaIEEE International Reliability Physics Symposium, pp. 6C.3.1-6C.3.4, 2013/04, Monterey, CA, USA
Contributions of Charge Sharing and Bipolar Effects to Cause or Suppress MCUs on Redundant Latches,pdfK. Zhang, and K. KobayashiIEEE International Reliability Physics Symposium, pp. SE.5.1-SE.5.4, 2013/04, Monterey, CA, USA
Impact of Random Telegraph Noise on CMOS Logic Delay Uncertainty,pdfT. Matsumoto, K. Kobayashi, and H. OnoderaInternational Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, 2013/03, Lake Tahoe, NV, USA
Impact of Cell Distance and Well Contact Density on Neutron-Induced Multiple Cell Upsets,pdf[URL]J. Furuta, K. Kobayashi, and H. OnoderaSilicon Errors in Logic - System Effects, 2013/03, Stanford, CA, USA
A Low-Power and Area-Efficient Radiation-Hard Redundant Flip-Flop: DICE ACFF ,pdf[URL]K. Kubota, M. Masuda, and K. KobayashiSilicon Errors in Logic - System Effects, 2013/03
Measurement Results of Substrate Bias Dependency on Negative Bias Temperature Instability Degradation in a 65 nm Process,pdf[URL]S. Tanihiro, M. Yabuuchi, and K. KobayashiComponents, Packaging, and Manufacturing Technology Symposium Japan, pp. 289-292, 2012/12, Kyoto, Japan
Measurement of Distance-dependent Multiple Upsets of Flip-Flops in 65nm CMOS Process,pdf[URL]J. Furuta, K. Kobayashi, and H. OnoderaInternational Workshop on Radiation Effects on Semiconductor Devices for Space Applications, pp. 154-156, 2012/12, Tsukuba, Japan
Impact of Random Telegraph Noise on CMOS Logic Delay Uncertainty under Low Voltage Operation,pdfT. Matsumoto, K. Kobayashi, and H. OnoderaInternational Electron Device Meeting, pp. 25.6.1-25.6.4, 2012/12, San Francisco, USA
Impact of Body-Biasing Technique on RTN-induced CMOS Logic Delay Uncertainty,pdfT. Matsumoto, K. Kobayashi, and H. OnoderaIEEE/ACM Workshop on Variability Modeling and Characterization, 2012/11, San Jose, CA
A 65 nm Low-Power Adaptive-Coupling Redundant Flip- Flops,pdfM. Masuda, K. Kubota, R. Yamamoto, J. Furuta, K. Kobayashi, and H. OnoderaThe conference on Radiation and its Effects on Components and Systems, pp. I-1.1-5, 2012/09, Biarritz, France
Impact of Body-Biasing Technique on RTN-induced Delay Fluctuation,pdfT. Matsumoto, K. Kobayashi, and H. OnoderaInternational Conference on Solid State Devices and Materials, pp. 1130-1131, 2012/09, Kyoto, Japan
Impact on Delay due to Random Telegraph Noise Under Low Voltage Operation in Logic Circuits,pdfS. Nishimura, T. Matsumoto, K. Kobayashi, and H. OnoderaInternational Conference on Solid State Devices and Materials, pp. 170-171, 2012/09, Kyoto, Japan
Effects of Neutron-Induced Well Potential Perturbation for Multiple Cell Upset of Flip-Flops in 65 nmJ. Furuta, R. Yamamoto, K. Kobayashi, and H. OnoderaIEEE Nuclear and Space Radiation Effects Conference, 2012/07, Miami, FL, USA
DARA: A Low-Cost Reliable Architecture Based on Unhardened Devices and its Case Study of Radiation Stress TestJ. Yao, Y. Nakashima, S. Okada, and K. KobayashiIEEE Nuclear and Space Radiation Effects Conference, 2012/07, Miami, FL, USA
Circuit Characteristic Analysis Considering NBTI and PBTI-Induced Delay Degradation,pdfM. Yabuuchi, and K. KobayashiInternational Meeting for Future of Electron Devices, Kansai, pp. 70-71, 2012/05, Osaka, Japan
Structure Dependence of Reduced Saturation Current Influenced by Source and Drain Resistances for 17 nm MOSFETs,pdfJ. Yoon, A. Hiroki, and K. KobayashiInternational Meeting for Future of Electron Devices, Kansai, pp. 92-93, 2012/05, Osaka, Japan
Evaluation of Parasitic Bipolar Effects on Neutron- Induced SET Rates for Logic Gates,pdfJ. Furuta, R. Yamamoto, K. Kobayashi, and H. OnoderaIEEE International Reliability Physics Symposium, pp. SE.5.1-SE5.5, 2012/04, Anaheim, CA
Parasitic Bipolar Effects on Soft Errors to Prevent Simultaneous Flips of Redundant Flip-Flops,pdfK. Zhang, R. Yamamoto, J. Furuta, K. Kobayashi, and H. OnoderaIEEE International Reliability Physics Symposium, pp. 5B.2.1-5B.2.4, 2012/04, Anaheim, CA
Degradation of Oscillation Frequency of Ring Oscillators Placed on a 90 nm FPGA,pdfS. Ishii, and K. KobayashiWorkshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 217 - 221, 2012/03, Beppu, Japan
Device-level Simulations of Parasitic Bipolar Mechanism on Preventing MCUs of Redundant Filp-Flops,pdfK. Zhang, R. Yamamoto, and K. KobayashiWorkshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 330 - 333, 2012/03, Beppu, Japan
Correlations between Well Potential and SEUs Measured by Well-Potential Perturbation Detectors in 65nm,pdfJ. Furuta, R. Yamamoto, K. Kobayashi, and H. OnoderaIEEE Asian Solid-State Circuits Conference, pp. 209-212, 2011/11, Jeju, Korea
Impact of RTN and NBTI on Synchronous Circuit Reliability,pdfT. Matsumoto, K. Kobayashi, and H. OnoderaIEEE/ACM Workshop on Variability Modeling and Characterization, 2011/11, San Jose, CA, USA
Multi-core LSI Lifetime Extension by NBTI-Recovery-based Self-healing,pdfT. Matsumoto, H. Makino, K. Kobayashi, and H. OnoderaInternational Conference on Solid State Devices and Materials, G-3-1, pp. 1045-1046, 2011/09, Nagoya, Japan
An Area-efficient 65 nm Radiation-Hard Dual-Modular Flip-Flop to Avoid Multiple Cell UpsetsR. Yamamoto, C. Hamanaka, J. Furuta, K. Kobayashi, and H. OnoderaIEEE Nuclear and Space Radiation Effects Conference, 2011/07, Las Vegas, NV, USA
An estimation of saturation current influenced by source and drain resistances for sub-20nm MOSFETs ,pdf[URL]J. Yoon, A. Hiroki, T. Sano, and K. KobayashiInternational Meeting for Future of Electron Devices, Kansai, pp. 56-57, 2011/05, Osaka, Japan
The Impact of RTN on Performance Fluctuation in CMOS Logic Circuits,pdf[URL]K. Ito, T. Matsumoto, S. Nishizawa, H. Sunagawa, K. Kobayashi, and H. OnoderaIEEE International Reliability Physics Symposium, pp. CR.5.1-CR.5.4, 2011/04, Monterey, CA, USA
Measurement of Neutron-induced SET Pulse Width Using Propagation-induced Pulse Shrinking,pdf[URL]J. Furuta, C. Hamanaka, K. Kobayashi, and H. OnoderaIEEE International Reliability Physics Symposium, pp. 5B.2.1-5B.2.5, 2011/04, Monterey, CA, USA
Variation-sensitive Monitor Circuits for Estimation of Die-to-Die Process Variation,pdf[URL]I. A.K.M Mahfuzul, A. Tsuchiya, K. Kobayashi, and H. OnoderaInternational Conference on Microelectronic Test Structure, pp. 153-157, 2011/04, Amsterdam, Germany
Modeling of Random Telegraph Noise under Circuit Operation - Simulation and Measurement of RTN-induced delay fluctuation,pdf[URL]K. Ito, T. Matsumoto, S. Nishizawa, H. Sunagawa, K. Kobayashi, and H. OnoderaInternational Symposium on Quality Electronic Design, pp. 22-27, 2011/03, Santa Clala, CA, USA
A 65nm Flip-Flop Array to Measure Soft Error Resiliency against High-Energy Neutron and Alpha Particles,pdf[URL]J. Furuta, C. Hamanaka, K. Kobayashi, and H. OnoderaAsia and South Pacific Design Automation Conference, pp. 83-84, 2011/01, Yokohama, Japan
Minimal Roll-Back Based Recovery Scheme for Fault Toleration in Pipeline Processors,pdf[URL]J. Yao, R. Watanabe, T. Nakada, H. Shimada, Y. Nakashima, and K. KobayashiPacific Rim International Symposium on Dependable Computing, pp. 237-238, 2010/12, Tokyo, Japan
Evaluation of FPGA design guardband caused by inhomogeneous NBTI degradation considering process variations,pdf[URL]M. Yabuuchi, and K. KobayashiInternational Conference on Field Programmable Technologies, pp. 417-420, 2010/12, Beijing, China
Circuit Performance Degradation on FPGAs Considering NBTI and Process Variations,pdfM. Yabuuchi, and K. KobayashiWorkshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 126-129, 2010/10, Taipei, Taiwan
A 65nm CMOS 400ns Measurement Delay NBTI-Recovery Sensor by Minimum Assist Circuit,pdfT. Matsumoto, H. Makino, K. Kobayashi, and H. OnoderaInternational Conference on Solid State Devices and Materials, G-3-4, 2010/09, Tokyo, Japan
A 65nm Bistable Cross-coupled Dual Modular Redundancy Flip-Flop Capable of Protecting Soft Errors on the C-element,pdf[URL]J. Furuta, C. Hamanaka, K. Kobayashi, and H. OnoderaVLSI Circuit Symposium, pp. 123-124, 2010/06, Honolulu, Hawaii, USA
Variability Characterization Using an RO-array Test Structure,pdfS. Nishizawa, K. Kobayashi, and H. OnoderaIEEE International Workshop on Design for Manufacturability & Yield, pp. 7-10, 2010/06, Anaheim, CA
Implementation and Evaluation of a Superscalar Processor Based on Dynamic Adaptive Redundant Architecture,pdfR. Watanabe, J. Yao, H. Shimada, and K. KobayashiSymposium on Low-Power and High-Speed Chips (COOL Chips), pp. 195, 2010/04, Yokohama, Japan
Measurement Results of Multiple Cell Upsets on a 65nm Tapless Flip-Flop Array,pdfJ. Furuta, K. Kobayashi, and H. OnoderaSilicon Errors in Logic - System Effects, 2010/03, Stanford, USA
Process-sensitive Monitor Circuits for Estimation of Die-to-Die Process Variability,pdfI. A.K.M Mahfuzul, A. Tsuchiya, K. Kobayashi, and H. OnoderaInternational Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, 2010/03, San Francisco, USA
A Stage-Level Recovery Scheme in Scalable Pipeline Modules for High Dependability,pdfJ. Yao, H. Shimada, and K. KobayashiInternational Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems, 2009/05, Hawaii
Effect of Regularity-Enhanced Layout on Printability and Circuit Performance of Standard Cells ,pdfH. Sunagawa, H. Terada, A. Tsuchiya, K. Kobayashi, and H. OnoderaInternational Symposium on Quality Electronic Design, pp. 195-200, 2009/03
A Stage-Level Recovery Scheme in Scalable Pipeline Modules for High DependabilityJ. Yao, H. Shimada, and K. KobayashiInternational Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems, 2009/03
Embedded Delay Detectors to Choose the Fastest Route in FPGAs for Variation-aware ReconfigurationY. Kume, Y. Sugihara, N. Lai Cam, K. Kobayashi, and H. OnoderaWorkshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 81, 2009/03
Soft-error Resiliency Evaluation on Delayed Multiple-modular Flip-FlopsJ. Furuta, Y. Moritani, K. Kobayashi, and H. OnoderaWorkshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 352-357, 2009/03
A Ring-Oscillator Array Circuit for Measurement and Modeling of Gate Delay VariabilityH. Terada, A. Tsuchiya, and K. KobayashiWorkshop on Test Structure Design for Variability Characterization, 2008/11
Performance Optimization by Track Swapping on Critical Paths Utilizing Random Variations for FPGAsY. Sugihara, Y. Kume, K. Kobayashi, and H. OnoderaInternational Conference on Field Programmable Logic and Applications, pp. 503-506, 2008/09
A Variation-aware Constant-Order Optimization Scheme Utilizing Delay Detectors to Search for Fastest Paths on FPGAsK. Kobayashi, Y. Kume, N. Lai Cam, Y. Sugihara, and H. OnoderaInternational Conference on Field Programmable Logic and Applications, pp. 107-112, 2008/09
Speed and Yield Enhancement by Track Swapping on Critical Paths Utilizing Random Variations for FPGAsY. Sugihara, Y. Kume, K. Kobayashi, and H. OnoderaInternational Symposium on Field-Programmable Gate Arrays , pp. 257-258, 2008/02
Estimation of Yield Enhancement by Critical Path Reconfiguration Utilizing Random Variations on Deep-submicron FPGAsY. Sugihara, Y. Kume, K. Kobayashi, and H. OnoderaWorkshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 183, 2007/10
A 90nm 8x16 FPGA Enhancing Speed and Yield Utilizing Within-Die VariationsY. Sugihara, M. Kotani, K. Katsuki, K. Kobayashi, and H. OnoderaAsia and South Pacific Design Automation Conference, pp. 122-123, 2007/01
A 90nm 8x16 LUT-based FPGA Enhancing Speed and Yield Utilizing Within-Die VariationsM. Kotani, K. Katsuki, K. Kobayashi, and H. OnoderaEuropean Solid-State Circuits Conference, pp. 110-113, 2006/09
A Yield and Speed Enhancement Technique Using Reconfigurable Devices against Within-Die Variations on the Nanometer RegimeK. Kobayashi, M. Kotani, K. Katsuki, Y. Takatsukasa, Y. Ogata, Y. Sugihara, and H. OnoderaInternational Conference on Field Programmable Logic and Applications, pp. 761-764, 2006/08
Deterministic/Probablistic Noise and Bit Error Rate Modeling on On-chip Global InterconnectY. Yuyama, K. Kobayashi, and H. OnoderaWorkshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 214-218, 2006/04
Extracting a Random Component of Variation from Measurement Results of a 90 nm LUT ArrayK. Katsuki, M. Kotani, K. Kobayashi, and H. OnoderaWorkshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 197-200, 2006/04
Measurement Results of Within-Die Variability on a 90nm LUT Array for Speed and Yield Enhancement of Reconfigurable DevicesK. Katsuki, M. Kotani, K. Kobayashi, and H. OnoderaAsia and South Pacific Design Automation Conference, pp. 110-111, 2006/01
A Yield and Speed Enhancement Scheme under Within-die Variations on 90nm LUT ArrayK. Katsuki, M. Kotani, K. Kobayashi, and H. OnoderaCustom Integrated Circuit Conference, pp. 601-604, 2005/09
A Resource-shared VLIW Processor Architecture for Area-efficient On-chip MultiprocessingK. Kobayashi, M. Aramoto, Y. Yuyama, A. Higuchi, and H. OnoderaAsia and South Pacific Design Automation Conference, pp. 619-622, 2005/01
An Analytical Power Model for Synthesized Register Files Considering address DependenciesA. Higuchi, K. Kobayashi, and H. OnoderaWorkshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 41-46, 2004/10
Dynamic Voltage and Frequency Scaling Techniques for Heterogeneous Multi-Processor Architecture in Future Nanometer TechnologiesY. Takatsukasa, K. Kobayashi, and H. OnoderaWorkshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 477-482, 2004/10
RTL/ISS Co-Modeling Methodology for Embedded Processor Using SystemCY. Yuyama, M. Aramoto, K. Kobayashi, and H. OnoderaInternational Symposium on Circuits and Systems, vol.V, pp. 305-308, 2004/05
An SoC Architecture and its Design Methodology using Unifunctional Heterogeneous Processor ArrayY. Yuyama, M. Aramoto, K. Kobayashi, and H. OnoderaAsia and South Pacific Design Automation Conference, pp. 737-742, 2004/01
Heterogeneous Processor Architecture and Its Design Methodology to Shorten the Design Period of Embedded SoCsY. Yuyama, M. Aramoto, K. Takai, K. Kobayashi, and H. OnoderaWorkshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 351-356, 2003/04
Measurement Results of On-chip IR-dropK. Kobayashi, J. Yamaguchi, and H. OnoderaCustom Integrated Circuit Conference, pp. 521-524, 2002/05
Hardware and Software Codesign with Using SystemC and BachY. Yuyama, K. Takai, K. Kobayashi, and H. OnoderaDATE Designers' Forum, pp. 30-34, 2002/03
ST: Perl Package for Simulation and Test EnvironmentK. Kobayashi, and H. OnoderaInternational Symposium on Circuits and Systems, vol.V, pp. 89-92, 2001/05
A Vector-Pipeline DSP for Low-Rate VideophonesK. Kobayashi, M. Eguchi, T. Iwahashi, T. Shibayama, S. Li, K. Takai, and H. OnoderaAsia and South Pacific Design Automation Conference, pp. 1-2, 2001/01
Vector Quantization Processor for Mobile Video CommunicationT. Iwahashi, T. Shibayama, M. Hashimoto, K. Kobayashi, and H. Onodera SOC/ASIC Conference, pp. 75-79, 2000/09
Physical Insights on Imprint and Application to Functional Memory with Ferroelectric Materials.Y. Fujii, D. Nagasawa, H. Nozawa, K. Kobayashi, and K. TamaruInternational Symposium on Integrated Ferroelectrics, pp. 274-275, 2000/03
Real Time Low Bit-Rate Video Coding Algorithm Using Multi-Stage Hierarchical Vector QuantizationK. Terada, M. Takeuchi, K. Kobayashi, H. Onodera, and K. TamaruInternational Conference on Acoustics, Speech, and Signal Processing, pp. 2673-2676, 1998/05
A Functional Memory Type Parallel Processor for Vector QuantizationK. Kobayashi, M. Kinoshita, M. Takeuchi, H. Onodera, and K. TamaruAsia and South Pacific Design Automation Conference, pp. 665-666, 1997/01
Memory-based Parallel Processor for Vector QuantizationK. Kobayashi, M. Kinoshita, M. Takeuchi, H. Onodera, and K. TamaruEuropean Solid-State Circuits Conference, pp. 184-187, 1996/09
A Bit-parallel Block-parallel Functional Memory Type Parallel Processor LSI for Fast Addition and MultiplicationK. Kobayashi, H. Onodera, and K. TamaruVLSI Circuit Symposium, pp. 61-62, 1995/06

International Confenrence (w/o Review)

titleauthortaken
Modeling of Random Telegraph Noise under Circuit Operation -Simulation and Measurement of RTN-Induced Delay FluctuationK. Ito, T. Matsumoto, S. Nishizawa, H. Sunagawa, K. Kobayashi, and H. OnoderaIEEE/ACM Workshop on Variability Modeling and Characterization, 2010/11, San Jose, CA, USA

Domestic Conference (w/ review)

titleauthortaken
Evaluation of Dynamic Characteristics of SiC MOSFET and JFET for Swiching at 13.56MHz,pdfS. Inamori, J. Furuta, and K. KobayashiWorkshop on Circuits and Systems, pp. 72-74, 2016/05
Analysis of Radiation-hard Standard Layout Structure,pdfK. Zhang, and K. KobayashiDesign Automation Symposium, pp. 115-120, 2013/08, Gihu, Japan
A Transistor Model for Transient Simulation of Aging Degradation with Verilog-A,pdfR. Kishida, and K. KobayashiDesign Automation Symposium, pp. 67-72, 2013/08, Gihu, Japan
Impact of NBTI and RTN on CMOS Digital Circuit and SRAM,pdfT. Matsumoto, K. Kobayashi, and H. OnoderaDesign Automation Symposium, pp. 151-156, 2012/08, Gero, Japan
Analytical Approach for NBTI-Induced Delay with RTN Model on FPGA Routing Architecture,pdfM. Yabuuchi, and K. KobayashiDesign Automation Symposium, pp. 189-194, 2011/09, Gero, Gifu, Japan
RTN-Induced Propagation Delay Fluctuation of Digital Circuits,pdfT. Matsumoto, K. Ito, K. Kobayashi, and H. OnoderaDesign Automation Symposium, pp. 87-92, 2011/08, Gero, Gifu, Japan
Design Methodology of On-Chip Power Distribution Network Considering Package Parasitic Resistance,pdfS. Nishizawa, K. Kobayashi, and H. OnoderaDesign Automation Symposium, pp. 45-50, 2011/08, Gero, Gifu, Japan
Evaluation of soft Error Rates based on the Parasitic Bipolar Effects from Circuit-Level Simulation,pdfJ. Furuta, C. Hamanaka, K. Kobayashi, and H. OnoderaDesign Automation Symposium, pp. 81-86, 2011/08, Gero, Gifu, Japan
Evaluation of Soft Error Immunity on Multiple Modular Flip Flops in Standard-cell-based ASICs,pdfM. Masuda, S. Okada, R. Yamamoto, J. Furuta, K. Kobayashi, and H. OnoderaWorkshop on Circuits and Systems, pp. 170-175, 2011/08, Awaji, Japan
Evaluation of the impact of a Random Telegraph Noise on Combinational Circuits,pdfK. Ito, T. Matsumoto, K. Kobayashi, and H. OnoderaDesign Automation Symposium, pp. 99-104, 2010/09, Toyohashi, Japan
Measurement Results of Neutron-Induced SET Pulse Width Using Propagation-Induced Pulse Narrowing in 65nm Process,pdfJ. Furuta, K. Kobayashi, and H. OnoderaDesign Automation Symposium, pp. 233-238, 2010/09, Toyohashi, Japan
Circuit Performance Degradation on FPGAs Considering NBTI and Process Variations,pdfM. Yabuuchi, and K. KobayashiDesign Automation Symposium, pp. 135-140, 2010/09, Toyohashi, Japan
Estimation of Process Parameter Variation using Delay Monitor Circuits,pdfI. A.K.M Mahfuzul, A. Tsuchiya, K. Kobayashi, and H. OnoderaDesign Automation Symposium, pp. 127-132, 2009/08, Kaga, Japan
Effect of Within-Die Variation on Sequencial Circuits Characteristics,pdfH. Sunagawa, A. Tsuchiya, K. Kobayashi, and H. OnoderaDesign Automation Symposium, pp. 85-90, 2009/08, Kaga, Japan
An Area/Delay Efficient Dual-modular Flip-Flop with Higher SEU/SET Immunity,pdfJ. Furuta, K. Kobayashi, and H. OnoderaWorkshop on Circuits and Systems, pp. 456-461, 2009/04, Karuizawa, Japan

Domestic Conference (w/o review)

titleauthortaken
Evaluation of Dynamic Characteristics of SiC MOSFET and JFET for Swiching at 13.56MHz,pdfS. Inamori, J. Furuta, and K. Kobayashi, 4-011, pp. 11, 2016/03
Methodology for Reduction of Timing Margin by Considering Correlation between Process Variation and BTI[URL]M. Yabuuchi, and K. KobayashiIEICE Technical Report (VLD), VLD2014-163, pp. 61-66, 2015/03, Naha, Japan
Initial Frequency Degradation on Ring Oscillators in 65-nm SOTB Process Caused by Plasma-Induced Damage,pdf[URL]A. Oshima, R. Kishida, M. Yabuuchi, and K. KobayashiIEICE Technical Report (ICD), ICD2014-48, pp. 93-98, 2014/08, Sapporo, Japan
A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14A Sleep Current using Reverse-Body-Bias Assisted 65nm SOTB CMOS Technology[URL]K. Ishibashi, N. Sugii, K. Usami, A. Hideharu, K. Kobayashi, P. Cong-Kha, H. Makiyama, Y. Yoshiki , H. Shinohara, T. Iwamatsu, Y. Yamaguchi, H. Oda, T. Hasegawa, S. Okanishi, H. Yanagita, S. Kamohara, M. Kadoshima, K. Maekawa, T. Yamashita, D. Le, T. Yomogita, M. Kudo, K. Kitamori, S. Kondo, and Y. ManzawaIEICE Technical Report (ICD), ICD2014-31, pp. 1-4, 2014/08, Sapporo, Japan
Reliability on Integrated Circuits -Details of Soft Errors -,pdf[URL]K. KobayashiIEICE Technical Report (ICD), ICD2013-134, pp. 81, 2014/01, Kyoto, Japan
Evaluation of Soft-error Tolenrance of Fully-Depleted Silicon on Insulators(FDSOI) by Circuit Simulations,pdfS. Kanda, and K. KobayashiElectronics Society Conference of IEICE, C-12-38, pp. 98, 2013/09, Fukuoka, Japan
Impact of Random Telegraph Noise on CMOS Logic Delay Uncertainty,pdf[URL]T. Matsumoto, K. Kobayashi, and H. OnoderaGeneral Conference of IEICE, C-12-54, pp. 125, 2013/03
Robust Redundant Circuit for Circuit Time-Dependent Deterioration by Reversing Resister Values,pdf[URL]S. Okada, J. Yao, H. Shimada, and K. KobayashiIEICE Technical Report (VLD), VLD2012-162, pp. 147-152, 2013/03, Naha, Japan
Soft-error Tolenrance of SOI Transisitors according to the Thickness of the BOX Layer,pdfK. Zhang, and K. KobayashiEngineering Sciences Society Conference of IEICE, A-3-8, pp. 55, 2012/09, Toyama, Japan
Characteristics of An NBTI Measurement Circuit to Reduce Switching Time between Degradation Mode and Recovery Mode,pdfA. Miki, T. Matsumoto, K. Kobayashi, and H. OnoderaElectronics Society Conference of IEICE, C-12-44, pp. 117, 2012/09, Toyama, Japan
Measurement of Multiple Cell Upset according to the Distances between Latches on Flip-Flops,pdfJ. Furuta, K. Kobayashi, and H. OnoderaEngineering Sciences Society Conference of IEICE, A-3-7, pp. 54, 2012/09, Toyama, Japan
An NBTI Measurement Circuit for Reduction of Switching Time between Degradation and Recovery Mode,pdfA. Miki, T. Matsumoto, K. Kobayashi, and H. OnoderaGeneral Conference of IEICE, C-12-24, 2012/03, Okayama, Japan
Soft Error Immunity on Redundant Flip-Flops with Heavy Ion Beams,pdfK. Murakami, R. Yamamoto, and K. KobayashiGeneral Conference of IEICE, C-12-14, 2012/03, Okayama, Japan
A 65-nm Radiation-Hard Flip-Flop Tolerant to Multiple Cell Upsets,pdf[URL]R. Yamamoto, C. Hamanaka, J. Furuta, K. Kobayashi, and H. OnoderaIEICE Technical Report (ICD), ICD2011-129, pp. 131-136, 2011/12, Osaka, Japan
Multi-core LSI Lifetime Extension by NBTI-Recovery-based Self-healing,pdfT. Matsumoto, H. Makino, K. Kobayashi, and H. OnoderaIEICE Technical Report (ICD), ICD2011-92, pp. 59-63, 2011/11, Miyazaki, Japan
Performance Evaluation of Soft-Error Tolerant Multiple Modular Processors Implemented with Redundant and Non-Redundant Flip-Flops ,pdfS. Okada, M. Masuda, J. Yao, H. Shimada, and K. KobayashiIEICE Technical Report (VLD), VLD2011-59, pp. 43-48, 2011/11, Miyazaki, Japan
Degradation of Oscillation Frequency of Ring Oscillators Placed on a 90 nm FPGA,pdfS. Ishii, and K. KobayashiIEICE Technical Report (VLD), VLD2011-55, pp. 19-24, 2011/11, Miyazaki, Japan
Soft Error Immunity on Multiple Modular Processors with Redundant or Non-Redundant Flip Flops,pdfS. Okada, M. Masuda, J. Yao, H. Shimada, and K. KobayashiEngineering Sciences Society Conference of IEICE, A-3-12, 2011/09, Sapporo, Japan
Analytical Approach for NBTI-Induced Degradation with RTN Model,pdfM. Yabuuchi, and K. KobayashiEngineering Sciences Society Conference of IEICE, A-3-9, 2011/09, Sapporo, Japan
Measurement Circuit for SET pulse width using Propagation-Induced Pulse Shrinking,pdfJ. Furuta, K. Kobayashi, and H. OnoderaElectronics Society Conference of IEICE, C-12-21, 2011/09
Measurement and Its Modeling of Digital Circuit Delay Degradation,pdfT. Matsumoto, K. Kobayashi, and H. OnoderaElectronics Society Conference of IEICE, C-12-20, 2011/09, Sapporo, Japan
Comparative specification with error resistance between DFF and Dual Modular Redundancy FFs,pdfK. Kubota, and K. KobayashiElectronics Society Conference of IEICE, C-12-22, 2011/09, Sapporo, Japan
Measurement Results of Variation of Dual Modular Redundancy Flip-Flop to Protect Soft Errors,pdfC. Hamanaka, R. Yamamoto, and K. KobayashiGeneral Conference of IEICE, A-3-4, 2011/03, Tokyo, Japan
A 65nm CMOS High-Speed and High-Fidelity NBTI Recovery Sensor,pdf[URL]T. Matsumoto, H. Makino, K. Kobayashi, and H. OnoderaIEICE Technical Report (ICD), ICD2010-104, pp. 55-58, 2010/12, Tokyo, Japan
A Dual-Modular Redundancy Flip-Flop Toralent to Soft Errors,pdfK. KobayashiEngineering Sciences Society Conference of IEICE, AT-1-4, 2010/09, Sakai, Japan
The Simple Layout TEG for Measuring Variation,pdfC. Hamanaka, and K. KobayashiEngineering Sciences Society Conference of IEICE, A-3-5, 2010/09, Sakai, Japan
A 65nm Bistable Cross-coupled Dual Modular Redundancy Flip-Flop Capable of Protecting Soft Errors on the C-element,pdfJ. Furuta, C. Hamanaka, K. Kobayashi, and H. OnoderaIEICE Technical Report (ICD), ICD2010-61, pp. 121-124, 2010/08, Sapporo, Japan
An Instruction Decomposition Scheme to Aid Fine-Grained Online Recovery in Pipeline ProcessorsH. Shimada, J. Yao, and K. KobayashiGeneral Conference of IEICE, D-10-6, 2010/03, Sendai, Japan
NBTI Degradation and Recovery Measurement by Subthreshold Leakage Current,pdfH. Makino, T. Matsumoto, K. Kobayashi, and H. OnoderaGeneral Conference of IEICE, C-12-68, 2010/03, Sendai, Japan
Generation Mechanism of SEU and MCU Caused by Parasitic Lateral Bipolar Transistors,pdfC. Hamanaka, J. Furuta, H. Makino, K. Kobayashi, and H. OnoderaIEICE Technical Report (VLD), VLD2009-103, pp. 25-30, 2010/03, Naha, Japan
A Circuit to Measure the Frequency Dependance of NBTI,pdfH. Makino, K. Kobayashi, and H. OnoderaElectronics Society Conference of IEICE, C-12-30, pp. 94, 2009/09, Niigata, Japan