Process scaling makes it possible to integrate billions of transistors on a single die. It is quite difficult to manufacture such small transistors with similar characteristics. Scaling down increases variations of transistor performance. In addition, high-k materials are said to affect variations seriously. Transistor performances are different die-to-die (D2D) and also within-die (WID). [1] reveals that WID variations are apparently observed in a 90nm process, which become dominant according to the process scaling[2-3]
Degradations of transistor performance by variations impacts gate delay. If the performance of transistors along some critical path becomes worse, a fabricated chip does not work correctly at the required speed. Finally it causes yield loss of ASICs. To avoid the loss we design implemented circuits with large amount of timing margins, but increase of the margin results in increase of power consumption and expansion of the circuit area.
We propose a yield and speed enhancement scheme against WID variations using the reconfigurable architecture. On reconfigurable devices, functions are allocated after manufacturing. In conventional reconfigurable hardwares, each reconfigurable functional block is considered to have the same performance. In the proposal method we measure WID variations after manufacturing, and allocate the functions suitably considering the measurement results. It enhances not only yield and speed, but also narrows timing margins.
There are many candidates of critical paths in a chip. If even one of these paths become slower by within-die (WID) variations, the fabricated chip become slower. Therefore WID variations uniformly degrade the performance of LSIs. That possibility increases as the transistor count. As the result, almost all fabricated chip may be slower and the yield drops significantly if WID variations become dominant.
The reconfigurable structure mitigates these performance degradation. Figure 2.1[Fundamental idea of the proposed yield enhancement scheme. Left: conventional cell-based fixed-structured ASICs. Right: proposed reconfigurable devices configurations of which are optimized as measured within-die variations.] shows the fundamental idea of the proposed speed and yield enhancement scheme compared with conventional cell-based fixed-structured ASICs. First of all, we fabricate a reconfigurable devices. WID variations are measured on every chip. Forecasting the variations is very difficult, but measuring them after manufacturing is much easier. When reconfiguration, functional blocks are placed according to the measured variations of each chip and their lengths of critical paths. That is to say, a functional block with longer critical path is allocated in the area of faster transistors and a block with shorter critical path is in the area of slower transistors. This method enhances not only yield and the maximum operating clock frequency of fabricated chips, but also slashes the timing margin by leveraging WID variations rather than compensating them.