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ŻҾ̿ز 裳ϩȥƥå
"֥åϩŬGaN HEMTñŸư3٥Ű楲ȥɥ饤" ĹΰϺ (2020ǯ) https://www.ieice.org/~kws/last_award.html
ز ƥLSI߷׵Ѹ DAݥ2019 ͥʸ
" "ĶưǤäǯ۸¬󥰥졼" ⹦ (ǯ8)
ز ƥLSI߷׵Ѹ DAݥ2019 ͥȯɽ
"ĶưǤäǯ۸¬󥰥졼" ⹦ (ǯ8)
ز ƥLSI߷׵Ѹ DAݥ2019 ͥȯɽ
" "ǥХߥ졼ѤFDSOIץˤå¤ΰ㤤ˤ륽եȥ顼δ۸ɾ" Ϻ (ǯ8)
ز ԥ塼ΰ辩ޡCSΰ辩ޡ
"ǥХߥ졼ѤFDSOIץˤå¤ΰ㤤ˤ륽եȥ顼δ۸ɾ" Ϻ (2020ǯ77) https://www.ipsj.or.jp/award/cs-award-2020.html
IEEE CEDA All Japan Joint Chapter Academic Research Award
"Evaluation of Radiation-hardened Structure for Stacked Transistors in FDSOI Process by Device Simulations", Ĺ(2019ǯ828)
"FDSOIץˤ륹å¤Υեȥ顼кˡƤӥǥХߥ졼Ѥɾ", Ĺ(2019ǯ
"FDSOIץˤ륹å¤Υեȥ顼кˡƤӥǥХߥ졼Ѥɾ", Ĺ(2019ǯ
"ǥХߥ졼Ѥ65nm FDSOIǥХѲȥեȥ顼ɾ", Ϻ(2019ǯ
ICMTS(International Conference on Microelectronic Test Structure) Best Paper Award
"Extracting BTI-induced Degradation without Temporal Factors by Using BTI-Sensitive and BTI-Insensitive Ring Oscillators", R. Kishida, T. Asuke, J. Furuta, and K. Kobayashi (2019ǯ)
"Radiation-Hardened Flip-Flops with Low-Delay Overhead Using PMOS Pass-Transistors to Suppress SET Pulses in a 65 nm FDSOI Process",Ĺ(2019ǯ225)
IEEE CEDA ǥ󥬥 ٥ ݥ
"ٱޤå¤ˤSOIץѥեȥ顼FFƤӼ¬ɾ", ݸ§ (2018ǯ126)
IEEE CEDA All Japan Joint Chapter Academic Research Award
FDSOIŬå¤ˤ륽եȥ顼кˡơɾٲˤƶɾ", ݲ (2018ǯ126)
ز ƥLSI߷׵Ѹ DAݥ2018 ͥݥȯɽ
"FDSOIץˤ륹å¤Υեȥ顼кˡƤӥǥХߥ졼Ѥɾ", Ĺ (2018ǯ830)
ز ƥLSI߷׵Ѹ DAݥ2018 ͥݥȯɽ
" ǥХߥ졼Ѥ65nm FDSOIǥХѲȥեȥ顼ɾ", Ϻ (2018ǯ830)
ز ƥLSI߷׵Ѹ DAݥ2017ͥȯɽ
"PMOSѥȥ󥸥Ѥ¿Ųѥեȥ顼FFƵڤɾ", Ĺ (2018ǯ829) https://www.ipsj.or.jp/award/sldm-award1.html
ز ԥ塼ΰ辩ޡCSΰ辩ޡ
PMOSѥȥ󥸥Ѥ¿Ųѥեȥ顼FFƵڤɾ, Ĺ (2018ǯ829) https://www.ipsj.or.jp/award/cs-awardee-2018.html
TPEC 2018 Second-Place Best Poster Award
"Design of gate driver monolithically integrated with power p-GaN HEMT based on E-mode GaN-on-Si technology", Yuki Yamashita (2018ǯ29)
ƥLSIΥå2017 ͥ
"FDSOIˤ¿Ųѥեȥ顼FF߷פɾ", Ĺ硤ݲĽᡤ½(2017ǯ517)
ŻҾ̿ز 29ϩȥƥå
"65nm FDSOIץˤƥ쥰եΥ¬ɾ", , 簴, μ, ½(2017ǯ511)
COOL Chips 20 Best Poster Award
Kodai Yamada, Haruki Maruoka, Jun Furuta, Kazutoshi Kobayashi, (2017ǯhttp://www.coolchips.org/2017/
IEEE EDS Kansai Chapter MFSK Award
Negative Bias Temperature Instability Caused by Plasma Induced Damage in 65 nm Bulk and Silicon On Thin BOX (SOTB) Processes in IRPS 2015, Ryo Kishida (2017ǯ130), MFSK_2017_kishida.pdf(450)
ز ƥLSI߷׵Ѹ DAݥ2015 ͥȯɽ
"65nmХ륯SOTBץǤΥƥˤ¤¬ɾ", μ, ½(2016ǯ914)
ز ƥLSI߷׵Ѹ ͥʸ
"65nmХ륯SOTBץǤΥƥˤ¤¬ɾ", μ, ½(2016ǯ914)
ز ƥLSI߷׵Ѹ DAݥ2014 ͥȯɽ
"󥰥졼ȯȿ¬꤫᤿ƥʥ᡼ˤӷǯɾ" μ簴Ϻ½ (2015ǯ827)
ز ƥLSI߷׵Ѹ DAݥ2014 ͥȯɽ
"󥰷ȯηǯФĤؤɾ" Ϻμ簴½ (2015ǯ827)
ز ƥLSI߷׵Ѹ DAݥ2014 ͥȯɽ
"65nm BOX-SOI ȥХ륯ץˤ SET ѥ륹۸ɾ" 󡦸ġᡦ½ (2015ǯ827)
ŻҾ̿ز ͥꥳե֥륷ƥʸ
"Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing" Hiroaki Konoura, Dawood Alnajjar (Osaka Univ.), Yukio Mitsuyama (Kochi Inst. Tech), Hajime Shimada(Nagoya U.), Kazutoshi Kobayashi (Kyoto Inst. Tech.), Hiroyuki Kanbara (ASTEM), Hiroyuki Ochi (Ritsumeikan U.), Takashi Imagawa, Kazutoshi Wakabayashi (NEC), Masanori Hashimoto, Takao Onoye (Osaka U.), Hidetoshi Onodera(Kyoto Univ.) (2015ǯ619)
ʿ簴 (2014/8/29) http://www.vdec.u-tokyo.ac.jp/designAward/welcome.html
Best Poster Paper Award of 2013 International Reliability Physics Symposium
"Contributions of Charge Sharing and Bipolar Effects to Cause or Suppress MCUs on Redundant Latches" by K. Zhang and K. Kobayashi (2014/06/03, https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6860573)
Ż̿ز áƥ Խưվ
Ż̿ز áƥ ׸
D2 Ϻ (2012/3/21)
ز ƥLSI߷׵Ѹ ͥʸ
"SETѥ륹ˤưɻߤٱեåץեåפΥեȥ顼θƤ" ½ (2009/8/26
"A 90nm 48x48 LUT-based FPGA Enhancing Spped and Yield Utilizing WIthin-Die Delay Variations" by K.Kobayashi et.al. (2009/5/23, https://www.ieice.org/jpn/about/rekidai/ronbunshou.html