- ز ƥLSI߷Ѹ DAݥࣲ ͥݥȯɽ
- "ɷ SEILA(եȥ顼å) ˤɾ", ķ, , δ, Ľ, ½(ǯ)
- ز ƥLSI߷Ѹ ǯ ƥ LSI ߷Ѹ ͥȯɽ
- "ȥ쥹ʬΥַȯѤǯݤμ¬ɾ", 轺 (), μ (ٻΩ), ½ (Թ), ã, μ, ʼ () (2024ǯ
- ŻҾ̿ز ICDֱͥ
- "եƥȤӥ㡼ȥåTLC NANDեåˤȡɡ̤Υǡѥ¸",߷, Ľ, ½(2024ǯ510)
- ǥͥݥ
- "եƥȤӥ㡼ȥåTLC NANDեåˤȡɡ̤Υǡѥ¸",߷(2023ǯ1117)
- ǥͥݥ
- "ȼͤˤ65nm bulkץˤPMOSڤNMOSȥSEU",ķ(2023ǯ17)
- IEEE CEDA All Japan Joint Chapter Design Gaia Best Paper Award
- "եȽťˤ륽եȥ顼Ψμȿ¸¬",(2023ǯ17)
- SLDM WIPͥ
- "ؽ˴Ť७ѥΥǥ벽˴ؤͻ", ò (Թ), ¼ (ζë), ë ƻ (Թ) (2023ǯ117)
- Excellent Student Paper Certificate of Honor of 2023 15th IEEE International Conference on ASIC
- "Ring Oscillators with Identical Circuit Structure to Measure Bias Temperature Instability", Daisuke Kikuta, Ryo Kishida, Kazutoshi Kobayashi (2023ǯ1027)
- IEEE CEDA All Japan Joint Chapter Academic Research Award
- "C-elementˤñΡȿž˶٤ѥեȥ顼եåץեåפ", ƣ, δ, Ľ, ½ (2023ǯ830), https://site.ieee.org/jc-ceda/awards/ieee-ceda-all-japan-joint-chapter-best-student-award/
- ز ƥLSI߷Ѹ DAݥ2022å̾
- "C-elementˤñΡȿž˶٤ѥեȥ顼եåץեåפ", ƣ, δ, Ľ, ½ (2023ǯ830)
- ز ƥLSI߷Ѹ DAݥ2022ͥȯɽ
- "C-elementˤñΡȿž˶٤ѥեȥ顼եåץեåפ", ƣ, δ, Ľ, ½ (2023ǯ830)
- 带2022ǯ٥ƥͥ
- ëƻ(2023ǯ61),https://www.kioxia.com/ja-jp/rd/collaboration/award-fy2022.html
- IEEE CEDA All Japan Joint Chapter Academic Research Award
- "ַưԤIoTץåŬFiCCԴȯեåץեåפμ¬ɾ",ͤ, ½, ͵Ƿ(2022ǯ1129), https://site.ieee.org/jc-ceda/awards/ieee-ceda-all-japan-joint-chapter-best-student-award/
- [带2022ǯ٥ƥͥ|https
- //www.kioxia.com/ja-jp/rd/collaboration/award-fy2022.html]:ëƻ(2023ǯ61)
- ز ƥLSI߷Ѹ WIPͥ
- "FDSOIץˤ륹å¤ѤեåץեåפΥեȥ顼μ¬ɾ", ëϺ δ졤 Ľᡤ ½ (2022ǯ1111)
- ز ƥLSI߷Ѹ DAݥ2022ͥݥ
- "FiCCԴȯեåץեåפѤַưǽʥμ¬ɾ, ͤ(2022ǯ91)
- ز ƥLSI߷Ѹ ͥȯɽ
- "TCADѤϩȥ쥤ȹ¤ˤեåץեåפΥեȥ顼ɾ", ë˨(2022ǯ831)
- 带2022ǯ٥ƥͥ
- ëƻ(2022ǯ61), https://www.kioxia.com/ja-jp/rd/collaboration/award-fy2022.html
- LSIȥƥΥåͥݥ
- () 濭(2022ǯ510)
- ŻҾ̿ز Ĺ ϫ
- ͤƣˡë˨ᡤδ2022ǯ310, https://www.ieice.org/kansai/student/kourou2021.html
- IEEE CEDA All Japan Joint Chapter (AJJC) Design Gaia Best Poster Award
- "Soft Errors on Flip-flops Depending on Circuit and Layout Structures Estimated by TCAD Simulations", ë˨(2021ǯ122), https://site.ieee.org/jc-ceda/awards/ieee-ceda-all-japan-joint-chapter-design-gaia-best-poster-award/
- ŻҾ̿ز 24쥯ȥ˥ƥ
- "ѲϩΥեȥ顼ιѲѤŪ",½(2021ǯ914)https://www.ieice.org/es/jpn/award/es.php
- ŻҾ̿زꥳե֥륷ƥฦֱͥ()
- "եȥ쥸ˤSRAMȥեå귿FPGAΥեȥ顼",ͺ(2021ǯ)
- ز ƥLSI߷Ѹ DAݥ2021ͥݥ
- "FDSOIץˤٱäɥȷեåץեåפΥեȥ顼μ¬ɾ", (2021ǯ93)
- ز ƥLSI߷Ѹ ͥʸ
- "FDSOIץˤ륬ɥȹ¤ѤեåץեåפΥեȥ顼μ¬ɾ", , ݸ§, Ľ, ½(2021ǯ9)
- ز ƥLSI߷Ѹ ͥȯɽ
- "FDSOIץˤ륬ɥȹ¤ѤեåץեåפΥեȥ顼μ¬ɾ", , ݸ§, Ľ, ½(2021ǯ9)
- IEEE CEDA All Japan Joint Chapter Academic Research Award
- "Evalution of Soft Error Tolerance by Flip-Flop Using Guard Gate", (2021ǯ91)
- ŻҾ̿ز 裳ϩȥƥå
- "֥åϩŬGaN HEMTñŸư3٥Ű楲ȥɥ饤" ĹΰϺ (2020ǯ1219, 2021ǯ826) https://www.ieice.org/~kws/last_award.html
- ز ƥLSI߷Ѹ DAݥ2019 ͥʸ
- " "ĶưǤäǯ۸¬졼" (ǯ8)
- ز ƥLSI߷Ѹ DAݥ2019 ͥȯɽ
- "ĶưǤäǯ۸¬졼" (ǯ8)
- ز ƥLSI߷Ѹ DAݥ2019 ͥȯɽ
- " "ǥХߥ졼ѤFDSOIץˤå¤ΰ㤤ˤ륽եȥ顼δ۸ɾ" Ϻ (ǯ8)
- ز ԥ塼ΰ辩ޡCSΰ辩ޡ
- "ǥХߥ졼ѤFDSOIץˤå¤ΰ㤤ˤ륽եȥ顼δ۸ɾ" Ϻ (2020ǯ77) https://www.ipsj.or.jp/award/cs-award-2020.html
- زǰ
- "FDSOIץˤ륹å¤Υեȥ顼кˡƤӥǥХߥ졼Ѥɾ",Ĺʣǯhttps://www.ipsj.or.jp/award/yamasita2019-detail.html#sldm
- IEEE CEDA All Japan Joint Chapter Academic Research Award
- "Evaluation of Radiation-hardened Structure for Stacked Transistors in FDSOI Process by Device Simulations", Ĺ(2019ǯ828)
- ز ƥ̣ӣ߷Ѹ2018ǯٺͥȯɽ
- "FDSOIץˤ륹å¤Υեȥ顼кˡƤӥǥХߥ졼Ѥɾ", Ĺ(2019ǯ
- ز ƥ̣ӣ߷Ѹ2018ǯͥȯɽ
- "FDSOIץˤ륹å¤Υեȥ顼кˡƤӥǥХߥ졼Ѥɾ", Ĺ(2019ǯ
- ز ƥ̣ӣ߷Ѹ2018ǯͥȯɽ
- "ǥХߥ졼Ѥ65nm FDSOIǥХѲȥեȥ顼ɾ", Ϻ(2019ǯ
- ICMTS(International Conference on Microelectronic Test Structure) Best Paper Award
- "Extracting BTI-induced Degradation without Temporal Factors by Using BTI-Sensitive and BTI-Insensitive Ring Oscillators", R. Kishida, T. Asuke, J. Furuta, and K. Kobayashi (2019ǯ)
- IEEE 澩
- "Radiation-Hardened Flip-Flops with Low-Delay Overhead Using PMOS Pass-Transistors to Suppress SET Pulses in a 65 nm FDSOI Process",Ĺ(2019ǯ225)
- IEEE CEDA All Japan Joint Chapter (AJJC) Design Gaia Best Poster Award
- "ٱޤå¤ˤSOIץѥեȥ顼FFƤӼ¬ɾ", ݸ§ (2018ǯ126) https://site.ieee.org/jc-ceda/awards/ieee-ceda-all-japan-joint-chapter-design-gaia-best-poster-award/
- IEEE CEDA All Japan Joint Chapter Academic Research Award
- FDSOIŬå¤ˤ륽եȥ顼кˡơɾٲˤƶɾ", ݲ (2018ǯ126)
- ز ƥLSI߷Ѹ DAݥ2018 ͥݥȯɽ
- "FDSOIץˤ륹å¤Υեȥ顼кˡƤӥǥХߥ졼Ѥɾ", Ĺ (2018ǯ830)
- ز ƥLSI߷Ѹ DAݥ2018 ͥݥȯɽ
- " ǥХߥ졼Ѥ65nm FDSOIǥХѲȥեȥ顼ɾ", Ϻ (2018ǯ830)
- ز ƥLSI߷Ѹ DAݥ2017ͥȯɽ
- "PMOSѥȥѤ¿Ųѥեȥ顼FFƵڤɾ", Ĺ (2018ǯ829) https://www.ipsj.or.jp/award/sldm-award1.html
- ز ԥ塼ΰ辩ޡCSΰ辩ޡ
- PMOSѥȥѤ¿Ųѥեȥ顼FFƵڤɾ, Ĺ (2018ǯ829) https://www.ipsj.or.jp/award/cs-awardee-2018.html
- TPEC 2018 Second-Place Best Poster Award
- "Design of gate driver monolithically integrated with power p-GaN HEMT based on E-mode GaN-on-Si technology", Yuki Yamashita (2018ǯ29)
- ƥLSIΥå2017 ͥ
- "FDSOIˤ¿Ųѥեȥ顼FF߷פɾ", Ĺ硤ݲĽᡤ½(2017ǯ517)
- ŻҾ̿ز 29ϩȥƥå
- "65nm FDSOIץˤƥ쥰եΥ¬ɾ", , 簴, μ, ½(2017ǯ511)
- COOL Chips 20 Best Poster Award
- Kodai Yamada, Haruki Maruoka, Jun Furuta, Kazutoshi Kobayashi, (2017ǯhttp://www.coolchips.org/2017/
- IEEE EDS Kansai Chapter MFSK Award
- Negative Bias Temperature Instability Caused by Plasma Induced Damage in 65 nm Bulk and Silicon On Thin BOX (SOTB) Processes in IRPS 2015, Ryo Kishida (2017ǯ130), MFSK_2017_kishida.pdf(672)
- ز ƥLSI߷Ѹ DAݥ2015 ͥȯɽ
- "65nmХ륯SOTBץǤΥƥˤ¤¬ɾ", μ, ½(2016ǯ914)
- ز ƥLSI߷Ѹ ͥʸ
- "65nmХ륯SOTBץǤΥƥˤ¤¬ɾ", μ, ½(2016ǯ914)
- ز ƥLSI߷Ѹ DAݥ2014 ͥȯɽ
- "졼ȯȿ¬꤫ƥʥˤӷǯɾ" μ簴Ϻ½ (2015ǯ827)
- ز ƥLSI߷Ѹ DAݥ2014 ͥȯɽ
- "ȯηǯФĤؤɾ" Ϻμ簴½ (2015ǯ827)
- ز ƥLSI߷Ѹ DAݥ2014 ͥȯɽ
- "65nm BOX-SOI ȥХ륯ץˤ SET ѥ륹۸ɾ" ġᡦ½ (2015ǯ827)
- ŻҾ̿ز ͥꥳե֥륷ƥʸ
- "Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing" Hiroaki Konoura, Dawood Alnajjar (Osaka Univ.), Yukio Mitsuyama (Kochi Inst. Tech), Hajime Shimada(Nagoya U.), Kazutoshi Kobayashi (Kyoto Inst. Tech.), Hiroyuki Kanbara (ASTEM), Hiroyuki Ochi (Ritsumeikan U.), Takashi Imagawa, Kazutoshi Wakabayashi (NEC), Masanori Hashimoto, Takao Onoye (Osaka U.), Hidetoshi Onodera(Kyoto Univ.) (2015ǯ619)
- VDECǥͥ
- ʿ簴 (2014/8/29) http://www.vdec.u-tokyo.ac.jp/designAward/welcome.html
- Best Poster Paper Award of 2013 International Reliability Physics Symposium
- "Contributions of Charge Sharing and Bipolar Effects to Cause or Suppress MCUs on Redundant Latches" by K. Zhang and K. Kobayashi (2014/06/03, https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=7112664)
- Ż̿ز áƥ Խưվ
- ½(2013/9/18
- Ż̿ز áƥ
- ½(2012/9/12
- ŻҾ̿زؽѾ
- D2 Ϻ (2012/3/21)
- ز ƥLSI߷Ѹ ͥʸ
- "SETѥ륹ˤưɻߤٱեåץեåפΥեȥ顼θƤ" ½ (2009/8/26
- ŻҾ̿زʸ
- "A 90nm 48x48 LUT-based FPGA Enhancing Spped and Yield Utilizing WIthin-Die Delay Variations" by K.Kobayashi et.al. (2009/5/23, https://www.ieice.org/jpn/about/rekidai/ronbunshou.html
Ϥ
http://www.kit.ac.jp/campus_index/life_fee/report/