//rectbegin
 reg equal_reg; //定義
//rectend
always @(posedge CLK or negedge RST)
 中略
    if(!RST)
      begin
	REGA<=0;REGB<=0;count<=0;
//rectbegin
	equal_reg<=0;//←初期化
//rectend
      end
 else if(equal)
      begin
	count<=0;
	REGB<=REGA+REGB;
//rectbegin
	equal_reg<=1; //← =が押されたら1にする. 
//rectend
     end
//rectbegin
  assign out=(equal_reg==0)?REGA:REGB;
   //↑ equal_reg==1ならREGBを出力(selector)
//rectend