Bit-parallel Block-parallel FMPP

The BPBP-FMPP LSI has functionalities of bit-parallel numerical and logical operations on internal two words. Since a CAM cell can execute logical operations on an external data and contents of words, we adopt the structure of a CAM cell as that of a FMPP cell. Using contents of another word as an external data, logical and numerical operations on two words can be performed.

We realize bit-parallel addition in combination with logical operations and a carry propagation using a Manchester carry chain\cite{CMOSVLSI} which propagates the carry in bit-parallel manner. The structure of a CAM cell enables search operations (content addressing) on the FMPP same as that of CAMs.

Primary operations on the BPBP-FMPP are summarized as follows.

  1. Bit-parallel block-parallel computations such as logical operations, addition, subtraction and multiplication.
  2. Search operation.
  3. Logical operations on flags.
  4. Parallel write operation.
  5. Multiple response resolution.
1kbit BPBP-FMPP LSI

Last modified: Thu Nov 5 14:56:13 JST 1998