ST: Perl Package for Simulation and Test

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ST is a Perl package for simulation and test. ST is almost compatible with Cadence STL. But ST has several innovative features. You can use ST for free of charge. It is distributed under GPL.

Now, you have to write various test benches for all simulators:

HDL, Netlist level
Circuit, Transistor level

ST is a solution!!

You can write your test bench with Perl!!
Your testbench can be converted to
- Logic and HDL simulators: Verilog Simulators
- Circuit simulators: SPICE, HSPICE, hsim,and any SPICE-compatible simulators.
- LSI testers: Agilent (Verigy) HP82000, HP83000, Hilevel Griffin

History

2025/2/5 (Version 10.00): You can use generated testbenches on the Cadence ADE_L simulation enviroment. Please see Section 7.3 in README-e.pdf

Download

ST-10.00.tar.gz

Document

README-e.pdf (Translated by DeepL)

Reference

Paper on the ISCAS 2001

Last modified: Wed Feb 5 08:27:16 JST 2025